Terence T Sych, 65Tampa, FL

6145043, Nov 7, 2000

Jun 5, 1998

9/092101

Terence Sych - Gilbert AZ
Byron R. Gillespie - Phoenix AZ
Ravi S. Rao - Phoenix AZ

Intel Corporation - Santa Clara CA

G06F 1300
G06F 700
H03K 1900

710126

An application accelerator (AA) unit that in one embodiment is part of an I/O processor (IOP) integrated circuit. The AAU includes logic circuitry for improving the performance of storage applications such as Redundant Array of Inexpensive Disks (RAID). A boolean unit performs operations such as exclusive-or (XOR) on multiple blocks of data to form the image parity block which is written to the redundant disk array. The AAU is associated with a memory-mapped programming interface that allows software executed by a core processor in the IOP to utilize the AAU for accelerating RAID storage applications as well as local memory DMA-type transfers, using the descriptor construct.

2015004, Feb 12, 2015

Aug 6, 2013

13/960775

Terence Sych - Chandler AZ, US

G06F 9/30

712 4

Instructions and logic provide SIMD vector population count functionality. Some embodiments store in each data field of a portion of n data fields of a vector register or memory vector, at least two bits of data. In a processor, a SIMD instruction for a vector population count is executed, such that for that portion of the n data fields in the vector register or memory vector, the occurrences of binary values equal to each of a first one or more predetermined binary values, are counted and the counted occurrences are stored, in a portion of a destination register corresponding to the portion of the n data fields in the vector register or memory vector, as a first one or more counts corresponding to the first one or more predetermined binary values.