Matthew B Severson, 45Oxford, OH

2022041, Dec 29, 2022

Jun 25, 2021

17/359350

- San Diego CA, US
Matthew SEVERSON - Austin TX, US
Kumar Kanti GHOSH - San Diego CA, US
Shishir JOSHI - Arvada CO, US

G06F 1/3296
H04L 12/10

Various embodiments may include methods and systems for power management of multiple chiplets within a system-on-a-chip (SoC). Various systems may include a power management integrated circuit (PMIC) configured to supply power to a first chiplet and a second chiplet across a shared power rail. The first chiplet may be configured to obtain first sensory information throughout the first chiplet. The second chiplet may be configured to obtain second sensory information throughout the second chiplet, and may be configured to transmit a voltage change message to the first chiplet based on the second sensory information. The first chiplet may be configured to transmit a power rail adjustment message to the PMIC based on the first sensory information and the voltage change message. The PMIC may be configured to adjust the voltage of at least one of the first chiplet and the second chiplet.

2022036, Nov 17, 2022

May 17, 2021

17/322402

- SAN DIEGO CA, US
Bharat Kumar RANGARAJAN - Bangalore, IN
Dipti Ranjan PAL - Irvine CA, US
Keith Alan BOWMAN - Morrisville NC, US
Matthew SEVERSON - Austin TX, US
Gordon LEE - Gilbert AZ, US

G06F 1/324
G06F 1/3296
H02H 9/02

In controlling power in a portable computing device (“PCD”), a power supply input to a PCD subsystem may be modulated with a modulation signal when an over-current condition is detected. Detection of the modulation signal may indicate to a processing core of the subsystem to reduce its processing load. Compensation for the modulation signal in the power supply input may be applied so that the processing core is essentially unaffected by the modulation signal.

2022031, Oct 6, 2022

Apr 1, 2021

17/220603

- SAN DIEGO CA, US
Matthew SEVERSON - Austin TX, US

G06F 1/3287
G06F 1/324
G06F 1/3296
G01R 21/133

In each of two or more pipelined subsystems, the relative amount of time that the processing cores are idle may be determined. If the idle ratio is below a threshold, the clock frequency and voltage may be adjusted using dynamic clock and voltage scaling (DCVS) based on a power limit. However, if the idle ratio exceeds the threshold, the clock frequency and voltage may be decreased without regard to the power limit.

2023004, Feb 16, 2023

Aug 16, 2021

17/402884

- San Diego CA, US
Matthew Severson - Austin TX, US
Haobo Zhao - San Diego CA, US

G06F 1/12
G06F 1/10
G06F 1/3206
G06F 13/20

Various embodiments include methods and systems for providing sleep clock edge-based global counter synchronization in a multiple-chiplet system. A system-on-a-chip (SoC) may include a first chiplet including a first chiplet global counter subsystem, and a second chiplet including a second chiplet global counter subsystem. The SoC may further include an interface bus communicatively coupling the first chiplet and the second chiplet, and a power management integrated circuit (PMIC) configured to supply a sleep clock to the first chiplet and the second chiplet. The first chiplet may be configured to transmit a global counter synchronization pulse trigger to the second chiplet across the interface bus. The second chiplet may be configured to load a global counter synchronization value into the second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock in response to receiving the global counter synchronization pulse trigger.

2023003, Feb 2, 2023

Jul 30, 2021

17/390215

- SAN DIEGO CA, US
Bohuslav RYCHLIK - SAN DIEGO CA, US
George PATSILARAS - SAN DIEGO CA, US
Prajakt KULKARNI - SAN DIEGO CA, US
Can HANKENDI - SAN DIEGO CA, US
Fahad ALI - SAN DIEGO CA, US
Jeffrey GEMAR - SAN DIEGO CA, US
Matthew SEVERSON - AUSTIN TX, US

G06F 13/16

The energy consumed by data transfer in a computing device may be reduced by transferring data that has been encoded in a manner that reduces the number of one “1” data values, the number of signal level transitions, or both. A data destination component of the computing device may receive data encoded in such a manner from a data source component of the computing device over a data communication interconnect, such as an off-chip interconnect. The data may be encoded using minimum Hamming weight encoding, which reduces the number of one “1” data values. The received data may be decoded using minimum Hamming weight decoding. For other computing devices, the data may be encoded using maximum Hamming weight encoding, which increases the number of one “1” data values while reducing the number of zero “0” values, if reducing the number of zero values reduces energy consumption.

2019005, Feb 14, 2019

Aug 8, 2018

16/058599

- San Diego CA, US
Raghukul TILAK - San Diego CA, US
Zhurang ZHAO - San Diego CA, US
Elisha ULMER - Kfar Baruch, IL
Richard Dominic WIETFELDT - San Diego CA, US
Matthew SEVERSON - Austin TX, US

G06F 13/42
G06F 9/448
G06F 9/30

Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals over a serial communication link. A method performed at a device coupled to a serial bus includes determining that GPIO state information corresponding to a physical GPIO pin or signal is available in an event register that has a first bit width and includes information identifying one or more devices associated with the event register, and exchanging the GPIO state information with the one or more devices over the serial bus. The GPIO state information may be transmitted over the serial bus in accordance with configuration information stored in the event register. The configuration information may include an address identifying the one or more devices. The configuration information may include addressing information identifying a target register in the one or more devices. The configuration information may include information identifying a mode of communication for transmitting the GPIO state information.