Inventors:
Paul Chang - Mahopac NY, US
Jie Deng - Wappingers Falls NY, US
Terrence B. Hook - Essex Junction VT, US
Sim Y. Loo - Rochester MN, US
Anda C. Mocuta - Hopewell Junction NY, US
Jae-Eun Park - Hopewell Junction NY, US
Kern Rim - Hopewell Junction NY, US
Xiaojun Yu - Hopewell Junction NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 17/50
G06F 17/18
G01R 31/26
Abstract:
A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.
