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Terry A Spooner, 6316 Saville Row, Mechanicville, NY 12118

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16 Saville Row, Mechanicville, NY 12118    518-6522508   

2 Cheshire Rdg, Clifton Park, NY 12065    518-3710281   

Halfmoon, NY   

2 Laurelwood Dr, New Fairfield, CT 06812    203-3120756   

Sterling, MA   

Long Lake, NY   

Boxborough, MA   

Poughkeepsie, NY   

2 Cheshire Rdg, Clifton Park, NY 12065   

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Degree: Graduate or professional degree

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Terry Spooner

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Us Patents

Reliable Low-K Interconnect Structure With Hybrid Dielectric

US Patent:
6917108, Jul 12, 2005
Filed:
Nov 14, 2002
Appl. No.:
10/294139
Inventors:
John A. Fitzsimmons - Poughkeepsie NY, US
Stephen E. Greco - LaGrangeville NY, US
Jia Lee - Beacon NY, US
Stephen M. Gates - Ossining NY, US
Terry Spooner - New Fairfield CT, US
Matthew S. Angyal - Stormville NY, US
Habib Hichri - Wappingers Falls NY, US
Glenn A. Biery - Staatsburg NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L023/48
H01L023/52
H01L029/40
US Classification:
257751, 257758
Abstract:
An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.

Copper Conductor

US Patent:
7119018, Oct 10, 2006
Filed:
Jul 9, 2004
Appl. No.:
10/887087
Inventors:
Michael W. Lane - Cortlandt Manor NY, US
Stefanie R. Chiras - Peekskill NY, US
Terry A. Spooner - New Fairfield CT, US
Robert Rosenberg - Cortlandt Manor NY, US
Daniel C. Edelstein - White Plains NY, US
Assignee:
International Buisness Machines Corporation - Armonk NY
International Classification:
H01L 21/44
US Classification:
438686, 438687, 438E23005
Abstract:
A conducting material comprising: a conducting core region comprising copper and from 0. 001 atomic percent to 0. 6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 atomic percent or greater of the one or more metals. The invention is also directed to a method of making a conducting material comprising: providing an underlayer; contacting the underlayer with a seed layer, the seed layer comprising copper and one or more metals selected from iridium, osmium and rhenium; depositing a conducting layer comprising copper on the seed layer, and annealing the conducting layer at a temperature sufficient to cause grain growth in the conducting layer, yet minimize the migration of the one or more alloy metals from the seed layer to the conducting layer. The method further comprises polishing the conducting layer to provide a polished copper surface material, and annealing the polished copper surface material at a temperature to cause migration of the one or more metals from the seed layer to the polished surface to provide an interfacial region in contact with a copper conductor core region. The interfacial region and the copper conductor core region comprise the one or more metals.

Back End Interconnect With A Shaped Interface

US Patent:
7122462, Oct 17, 2006
Filed:
Nov 21, 2003
Appl. No.:
10/707122
Inventors:
Lawrence A. Clevenger - LaGrangeville NY, US
Andrew P. Cowley - Wappingers Falls NY, US
Timothy J. Dalton - Ridgefield CT, US
Mark Hoinkis - Fishkill NY, US
Steffen K. Kaldor - Fishkill NY, US
Erdem Kaltalioglu - Fishkill NY, US
Kaushik A. Kumar - Beacon NY, US
Douglas C. La Tulipe, Jr. - Danbury CT, US
Jochen Schacht - Hsinchu, TW
Andrew H. Simon - Fishkill NY, US
Terry A. Spooner - New Fairfield CT, US
Yun-Yu Wang - Poughquag NY, US
Clement H. Wann - Carmel NY, US
Chih-Chao Yang - Beacon NY, US
Assignee:
International Business Machines Corporation - Armonk NY
Infineon Technologies, AG - Munich
International Classification:
H01L 21/4763
US Classification:
438622, 438637
Abstract:
An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

Reliable Low-K Interconnect Structure With Hybrid Dielectric

US Patent:
7135398, Nov 14, 2006
Filed:
Jul 29, 2004
Appl. No.:
10/901868
Inventors:
John A. Fitzsimmons - Poughkeepsie NY, US
Stephen E. Greco - LaGrangeville NY, US
Jia Lee - Beacon NY, US
Stephen M. Gates - Ossining NY, US
Terry Spooner - New Fairfield CT, US
Matthew S. Angyal - Stormville NY, US
Habib Hichri - Wappingers Falls NY, US
Glenn A. Biery - Staatsburg NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/4763
US Classification:
438618, 438778, 438780, 438782, 438631, 257E21257, 257E21259, 257E21261
Abstract:
An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.

Plating Seed Layer Including An Oxygen/Nitrogen Transition Region For Barrier Enhancement

US Patent:
7215006, May 8, 2007
Filed:
Oct 7, 2005
Appl. No.:
11/245540
Inventors:
Chih-Chao Yang - Poughkeepsie NY, US
Simon Gaudet - Montreal, CA
Christian Lavoie - Ossining NY, US
Shom Ponoth - Fishkill NY, US
Terry A. Spooner - New Fairfield CT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 23/58
US Classification:
257632, 257347, 257762, 257E21006, 257E21094, 257E21218, 257E21319
Abstract:
An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement. The plating seed layer may include Ru, Ir or alloys thereof, and the interconnect conductive material may include Cu, Al, AlCu, W, Ag, Au and the like. Preferably, the interconnect conductive material is Cu or AlCu. In more specific terms, the present invention provides a single seeding layer which includes an oxygen/nitrogen transition region sandwiched between top and bottom seed regions. The presence of the oxygen/nitrogen transition region within the plating seed layer dramatically enhances the diffusion barrier resistance of the plating seed.

Method Of Forming Low Resistance And Reliable Via In Inter-Level Dielectric Interconnect

US Patent:
7223691, May 29, 2007
Filed:
Oct 14, 2004
Appl. No.:
10/965031
Inventors:
Cyril Cabral, Jr. - Ossining NY, US
Lawrence A. Clevenger - LaGrangeville NY, US
Timothy J. Dalton - Ridgefield CT, US
Patrick W. DeHaven - Poughkeepsie NY, US
Chester T. Dziobkowski - Hopewell Junction NY, US
Terry A. Spooner - New Fairfield CT, US
Kwong Hon Wong - Wappingers Falls NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/44
US Classification:
438659, 438597, 438658, 438687, 257E21575
Abstract:
A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) layer surface; and, performing a low energy ion implant of an inert gas (Nitrogen) into the exposed metal underneath; and, depositing a refractory liner into the walls and bottom via structure which will have a lower contact resistance due to the presence of the proceeding inert gas implantation. Preferably, the inert Nitrogen gas reacts with the underlying exposed Copper metal to form a thin layer of CuN.

Maintaining Uniform Cmp Hard Mask Thickness

US Patent:
7253098, Aug 7, 2007
Filed:
Aug 27, 2004
Appl. No.:
10/711145
Inventors:
Kaushik Arun Kumar - Beacon NY, US
Stephen Edward Greco - LaGrangeville NY, US
Shom Ponoth - Fishkill NY, US
Terry Allen Spooner - New Fairfield CT, US
David L. Rath - Stormville NY, US
Wei-Tsu Tseng - Hopewell Junction NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/4763
US Classification:
438637, 438692, 257E21577
Abstract:
A chemical mechanical polishing (CMP) step is used to remove excess conductive material (e. g. , Cu) overlying a low-k or ultralow-k interlevel dielectric layer (ILD) layer having trenches filled with conductive material, for a damascene interconnect structure. A reactive ion etch (RIE) or a Gas Cluster Ion Beam (GCIB) process is used to remove a portion of a liner which is atop a hard mask. A wet etch step is used to remove an oxide portion of the hard mask overlying the ILD, followed by a final touch-up Cu CMP (CMP) step which chops the protruding Cu patterns off and lands on the SiCOH hard mask. In this manner, processes used to remove excess conductive material substantially do not affect the portion of the hard mask overlying the interlevel dielectric layer.

Method Of Making A Semiconductor Structure With A Plating Enhancement Layer

US Patent:
7341948, Mar 11, 2008
Filed:
Jan 17, 2006
Appl. No.:
11/306930
Inventors:
Shom Ponoth - Fishkill NY, US
Steven Shyng-Tsong Chen - Patterson NY, US
John Anthony Fitzsimmons - Poughkeepsie NY, US
Terry Allen Spooner - New Fairfield CT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/44
US Classification:
438687, 438679, 438681, 257E2117, 257E21304, 257E2101
Abstract:
Disclosed is a method of making a semiconductor structure, wherein the method includes forming an interlayer dielectric (ILD) layer on a semiconductor layer, forming a conductive plating enhancement layer (PEL) on the ILD, patterning the ILD and PEL, depositing a seed layer into the pattern formed by the ILD and PEL, and then plating copper on the seed layer. The PEL serves to decrease the resistance across the wafer so to facilitate the plating of the copper. The PEL preferably is an optically transparent and conductive layer.

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