Tom Q Chi, 63Round Rock, TX

5378926, Jan 3, 1995

Jan 10, 1994

8/179898

Tom Y. Chi - San Gabriel CA
Brook D. Raymond - Hermosa Beach CA

Hughes Aircraft Company - Los Angeles CA

H01L 2348
H01L 2962
H01L 2940

257767

A gallium arsenide monolithic microwave integrated circuit (MMIC) chip (12) has microelectronic devices (16, 18) formed on a frontside surface (12a), and via holes (12c, 12d) formed through the chip (12) from the frontside surface (12a) to a backside surface (12b). The backside surface (12b) of the chip (12) is bonded to a molybdenum carrier (14) by an eutectic gold/tin alloy (20). A barrier layer (22) including a refractory metal nitride material (22a) is sputtered onto the backside surface (12b) and into the via holes (12c, 12d) of the chip (12) prior to bonding. The barrier layer (22) blocks migration of tin from the eutectic gold-tin alloy (20) through the via holes (12c,-12d) to the frontside surface (12a) of the chip (12) during the bonding operation, thereby preventing migrated tin from adversely affecting the microelectronic devices (16, 18).

5556797, Sep 17, 1996

May 30, 1995

8/453676

Tom Y. Chi - San Gabriel CA
Liping D. Hou - Rancho Palos Verdes CA
Kusol Lee - Gardena CA
Danny Li - Torrance CA
Ishver K. Naik - Rancho Palos Verdes CA
Tom Quach - Torrance CA

Hughes Aircraft Company - Los Angeles CA

H01L 218258

437405

A method of fabricating a self-aligned double gate recess profile in a semiconductor substrate is disclosed in which a first mask layer is formed over the substrate. A second mask layer having an opening is formed over the first mask layer. An opening at least as wide as the second mask layer's opening is formed through the first mask layer to expose the substrate beneath the second mask layer's opening. A first recess is etched in the semiconductor through the second mask layer's opening. The first mask layer's opening is then uniformly expanded and a wider recess, aligned to the first recess, is then formed in the semiconductor. The method is particularly applicable to the formation of self-aligned gate and channel recesses in a GaAs MESFET.

5350662, Sep 27, 1994

Jan 13, 1994

8/181371

Tom Y. Chi - San Gabriel CA

Hughes Aircraft Company - Los Angeles CA

G03F 720

430313

A "maskless" process is provided for the formation of a refractory metal layer (22b), such as titanium, in via holes (18) through GaAs wafers (12) to contact microwave monolithic integrated circuit (MMIC) devices (10) formed on the front surface (12a) thereof. The process of the invention, which prevents AuSn solder (28) from filling up the holes during a subsequent eutectic AuSn bonding of the device to a metal carrier (30), such as molybdenum, utilizes the difference of resist thickness on the GaAs backside surface (12b) and in the via holes, so that the resist (24b) remaining in the via holes after removing the resist (24a) over the GaAs back surface serves as a mask in etching the refractory metal layer (22a) over the GaAs back surface. The process of the invention does not require any masks, and results in self-alignment of the refractory metal to the via hole. The process is simple and results in high yield of the MMIC devices on GaAs chips (26).

5436201, Jul 25, 1995

May 28, 1993

8/068871

Tom Y. Chi - San Gabriel CA
Danny Li - Torrance CA
Liping Hou - Rancho Palos Verdes CA
Tom Quach - Torrance CA

Hughes Aircraft Company - Los Angeles CA

H01L 218252

437203

A semiconductor substrate is etched in a two-step sequence, with two different liquid etchants that have different lateral etch rates. The relative time periods for which the etchants are applied are selected to achieve a close match between the actual etch profile and the desired profile. The process is particularly applicable to the formation of a gate recess in a GaAs MESFET for high power amplification.

5539228, Jul 23, 1996

Feb 7, 1995

8/385386

Tom Y. Chi - San Gabriel CA

Hughes Aircraft Company - Los Angeles CA

H01L 2980
H01L 31112

257283

A monolithic-microwave-integrated-circuit (MMIC) metal-semiconductor-field-effect (MESFET) transistor (40) or other type of field-effect transistor has a double-recessed channel region (32,42) with a gate recess (42) formed in a channel recess (32). The channel recess (32) is offset toward the drain (16) as far as possible without shorting the channel recess (32) to the drain (16) to increase the transistor breakdown voltage. The gate recess (42) is offset toward the source (14) as far as possible without causing the gate-source capacitance to increase, thereby reducing the transistor source resistance.

5156998, Oct 20, 1992

Sep 30, 1991

7/767949

Tom Y. Chi - San Gabriel CA
Brook D. Raymond - Hermosa Beach CA

Hughes Aircraft Company - Los Angeles CA

H01L 2158

437209

A gallium arsenide monolithic microwave integrated circuit (MMIC) chip (12) has microelectronic devices (16,18) formed on a frontside surface (12a), and via holes (12c,12d) formed through the chip (12) from the frontside surface (12a) to the backside surface (12b). The backside surface (12b) of the chip (12) is bonded to a molybdenum carrier (14) by an eutectic gold/tin alloy (20). A barrier layer (22) including a refractory metal nitride material (22a) is sputtered onto the backside surface (12b) and into the via holes (12c,12d) of the chip (12) prior to bonding. The barrier layer (22) blocks migration of tin from the eutectic gold/tin alloy (20) through the via holes 12c,-12d) to the frontside surface (12a) of the chip (12) during the bonding operation, thereby preventing migrated tin from adversely affecting the microelectronic devices (16,18 ).

5283452, Feb 1, 1994

Feb 14, 1992

7/837448

Yi-Chi Shih - Torrance CA
David C. Wang - Rancho Palos Verdes CA
Huy M. Le - Monterey Park CA
Vincent Hwang - Long Beach CA
Tom Y. Chi - San Gabriel CA

Hughes Aircraft Company - Los Angeles CA

H01L 29812

257277

A distributed cell field-effect transistor (FET) amplifier (40) includes a plurality of parallel, elongated source (46a) and drain (46b) regions of individual FET unit cells (46) formed in a substrate (42) in transverse alternating relation, with a plurality of elongated channel regions (46c) being formed between and parallel to adjacent source (46a) and drain (46b) regions respectively. A source foot (48) and a drain foot (50) extend perpendicular to the source (46a) and drain (46b) regions on opposite longitudinally spaced sides thereof respectively. A gate foot (52) extends parallel to the source (48) and drain (50) feet, between the source foot (48) and the cells (46). Source (54) and drain (56) pads and gate (58) fingers extend from the source (48), drain (50) and gate (52) feet into electrical connection with the respective source (46a), drain (46b) and gate ( 46c) regions respectively. The source pads (54) include airbridge portions (54b) which extend over the gate foot (52) without making contact therewith. A fixed tuning circuit (70) is connected between the gate foot (52) and source foot (48), including an inductive stub (72) having a first end connected to the gate foot (52) and a second end, and a capacitor (74) having a first plate (74a) which is integral with the source foot (48) and a second plate connected to the second end of the stub (72).

5705432, Jan 6, 1998

Dec 1, 1995

8/566197

Kusol Lee - Gardena CA
Tom Quach - Torrance CA
Danny Li - Torrance CA
Liping D. Hou - Rancho Palos Verdes CA
Sam Chung - Costa Mesa CA
Tom Y. Chi - San Gabriel CA

Hughes Aircraft Company - Los Angeles CA

H01L 21465

437228

A unique photoresist process is provided which achieves clean and complete lift-off of a thin film layer such as a sputtered thin film formed on a photoresist which is formed above a semiconductor substrate. The process of the present invention relies on a reentrant photoresist profile which breaks the continuity of the thin film layer. Accordingly, the process of the present invention ensures a clean lift-off. The desired photoresist profile which breaks the continuity of the thin film layer can be obtained by a typical photoresist process preceded by an oxidation process that takes place on the surface of the semiconductor substrate. The oxidation process provides a thin native oxide layer with thickness ranging from about 30 to 50. ANG. No extra processing steps involving dielectric film deposition and etch are required to achieve clean lift-off. Nevertheless, the process of the present invention ensures the clean lift-off of the thin film layer.