Weidong Li, 6035231 Cornish Dr, Fremont, CA 94536

7071939, Jul 4, 2006

Aug 12, 2004

10/916995

Weidong Li - Cupertino CA, US

Broadcom Corporation - Irvine CA

G06T 11/00

345428

A method of presenting a selected portion of graphical images within a wireless terminal that includes receiving an original graphical image, having a source resolution, to be presented on a display screen. The native pixel resolution of the display screen may differ from that of the original graphical image. A complex decimation pattern when applied to the selected portion of the image allows the selected portion of the original graphical image to be resized from the source resolution to a decimated resolution operable to be displayed within the native resolution of the display screen. Decimated pixels need not be further processed to reduce the processing requirements imposed on the system processor. Operations normally associated with the decimated portions of the image may be offloaded from the processing module to improve system efficiency.

7365748, Apr 29, 2008

Aug 12, 2004

10/917006

Weidong Li - Cupertino CA, US

Broadcom Corporation - Irvine CA

G06T 11/00

345428, 382243, 345698

A method of presenting graphical images within a wireless terminal that includes receiving an original graphical image, having a source resolution, to be presented on a display screen. The native pixel resolution of the display screen may differ from that of the original graphical image. A complex decimation pattern when applied to the image allows the original graphical image to be resized from the source resolution of the original graphical image to a decimated resolution operable to be displayed within the native resolution of the display screen. Decimated pixels need not be further processed to reduce the processing requirements imposed on the system processor. Operations normally associated with the decimated portions of the image may be offloaded from the processing module to improve system efficiency.

7420560, Sep 2, 2008

Jun 27, 2006

11/426644

Weidong Li - Cupertino CA, US

Broadcom Corporation - Irvine CA

G06T 11/00

345428, 345603, 382243

A method of presenting a selected portion of graphical images within a wireless terminal that includes receiving an original graphical image, having a source resolution, to be presented on a display screen. The native pixel resolution of the display screen may differ from that of the original graphical image. A complex decimation pattern when applied to the selected portion of the image allows the selected portion of the original graphical image to be resized from the source resolution to a decimated resolution operable to be displayed within the native resolution of the display screen. Decimated pixels need not be further processed to reduce the processing requirements imposed on the system processor. Operations normally associated with the decimated portions of the image may be offloaded from the processing module to improve system efficiency.

7463871, Dec 9, 2008

Dec 9, 2005

11/298431

Weidong Li - Los Gatos CA, US

Broadcom Corporation - Irvine CA

H04B 1/18
H04B 7/00

455130, 455140, 4551832, 4552342, 455333, 455337, 375147, 375340

An integrated circuit radio receiver includes radio frequency (“RF”) front end circuitry for receiving and transmitting digital data received through a wireless interface. A baseband processor is operable to process the digital data received through the wireless interface. A first logic is operable to provide a first level of digital filtering for a first received digital data signal format. A second logic is operable to provide the first level of digital filtering and derotation for a second received digital data signal format. A third logic is operable to provide a second level of digital filtering for a third received digital data signal format wherein the second level of digital filtering is reduced in comparison to the first level of digital filtering. Selection logic is operable to select between the first, second and third logic for processing the digital data received through the wireless interface.

7641124, Jan 5, 2010

Jun 30, 2006

11/479897

Kerry D. Brown - Portola Valley CA, US
David K. Pariseau - Los Altos CA, US
Weidong Li - Mountain View CA, US
Edgar M. Williams - Palo Alto CA, US
Joyce Thompson - Menlo Park CA, US

Qsecure, Inc. - Los Altos CA

G06K 19/06

235493, 235492, 235451

A Q-Chip MEMS magnetic device comprises a thin-film electronic circuit for implantation in the Track-2 area of a magnetic stripe on the back of a credit card. The Q-Chip MEMS magnetic device periodically self-generates new sub-sets of magnetic data that are to be read in combination with other magnetic data that is permanently recorded in the surrounding surface of the magnetic stripe. A collocated battery and microcontroller provide operating power and new data for magnetic bit updates. A swipe sensor triggers such updates by sensing electrical contact with a legacy card reader. Several thin-film coils of wire are wound end-to-end around a common, flat, ferrous core. These are driven by the microcontroller. In one instance, such core comprises “hard” magnetic material with a coercivity of 200-300 Oersteds. Magnetic data written from the corresponding adjacent coils will persist for later readings by a legacy card reader.

7681065, Mar 16, 2010

Sep 3, 2004

10/933988

Weidong Li - Cupertino CA, US

Broadcom Corporation - Irvine CA

G06F 1/10

713600

Certain embodiments of the invention may be found in a method and system for processing messages. Aspects of the method may comprise receiving at least one signal on a chip that controls switching from a core processor to a DSP. At least a first bus that couples the core processor to a message processor and at least a first clock signal that clocks the core processor may be switched. At least a second bus that couples the DSP to the message processor and at least a second clock signal that clocks the DSP may be switched. When a loss of clock signal from the core processor or the DSP to the message processor is detected, a third clock signal for clocking the message processor may be generated. The message processor switch significantly reduces the amount of bandwidth utilized for transfer of data between the core processor and the DSP and provides incremental redundancy (IR) without high hardware cost and software MIPS, thereby providing significant improvement in system performance.

7688334, Mar 30, 2010

Feb 14, 2006

11/353900

Weidong Li - Los Gatos CA, US

Broadcom Corporation - Irvine CA

G06T 15/00

345604, 345503, 345582, 348453, 348488, 382298

Methods and systems for video format transformation in a mobile terminal having a video display may include converting interleaved YUV 4:2:2 color space video data to YUV 4:2:0 color space video data as the interleaved YUV 4:2:2 color space video data is received. The conversion may use Y, U, and V components in the interleaved YUV 4:2:2 color space video data for a horizontal line of video data. The conversion may also use only a Y component in the interleaved YUV 4:2:2 color space video data for a previous horizontal line or a successive horizontal line of video data. The converted 4:2:0 color space video data may be transferred to memory via, for example, direct memory access. The YUV 4:2:0 color space video data may be transferred to the memory as, for example, 32-bit words.

7707441, Apr 27, 2010

Oct 22, 2004

10/971651

Weidong Li - Cupertino CA, US

Broadcom Corporation - Irvine CA

G06F 1/26

713320

Certain aspects of reducing power consumption in communication devices may comprise deasserting a signal indicating that an on-chip UART may be ready to receive data. The deasserted signal may be asserted when the on-chip UART is not ready to receive data. The deasserted signal and asserted signal may be a RTS signal or a CTS signal. The signal may be deasserted when an on-chip processor wakes up from a low power state. The deasserted signal may be asserted when an on-chip processor enters a low power state. The on-chip UART may be adapted to receive and process data from an off-chip processor when the signal is deasserted. The data may be queued externally to the on-chip UART by an off-chip processor when the deasserted signal is asserted. The on-chip UART may be adapted to receive an interrupt signal that causes it to wake up from a low power state.