BackgroundCheck.run
Search For

Thomas R Trent Deceased5725 Vesper Ave, Van Nuys, CA 91411

Known as:
Tom R Trent Tr R Trent Trent Tom

Thomas Trent Phones & Addresses

5725 Vesper Ave, Van Nuys, CA 91411   

1226 Rossmoor Pkwy, Walnut Creek, CA 94595   

1228 Rossmoor Pkwy, Walnut Creek, CA 94595   

6970 California Ave SW, Seattle, WA 98136   

513 Princeton Rd, San Mateo, CA 94402   

Lafayette, CA   

Citrus Heights, CA   

Sacramento, CA   

Berkeley, CA   

Get Report
Control this profile

Mentions for Thomas R Trent

Thomas Trent resumes & CV records

Resumes

Thomas Trent Photo 47

Thomas Trent

Thomas Trent Photo 48

Thomas Trent

Thomas Trent Photo 49

Thomas Trent

Skills:
Process Improvement, Microsoft Word, Microsoft Office, Microsoft Excel, Negotiation, New Business Development, Manufacturing
Thomas Trent Photo 50

Thomas Trent

Thomas Trent Photo 51

Thomas Trent

Publications & IP owners

Us Patents

Embedded Non-Volatile Memory

US Patent:
2016035, Dec 1, 2016
Filed:
Aug 15, 2016
Appl. No.:
15/236600
Inventors:
- San Jose CA, US
Mac D. APODACA - San Jose CA, US
Thomas Michael TRENT - Tucson AZ, US
James Juen HSU - Saratoga CA, US
International Classification:
H01L 27/24
H01L 45/00
Abstract:
The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F.sup.2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

Embedded Non-Volatile Memory

US Patent:
2016002, Jan 21, 2016
Filed:
Jun 8, 2015
Appl. No.:
14/733919
Inventors:
- Amsterdam, NL
Mac D. APODACA - San Jose CA, US
Thomas Michael TRENT - Nashua NH, US
James Juen HSU - Saratoga CA, US
International Classification:
H01L 27/24
H01L 45/00
Abstract:
The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F.sup.2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

Embedded Non-Volatile Memory

US Patent:
2014015, Jun 12, 2014
Filed:
Dec 7, 2012
Appl. No.:
13/707895
Inventors:
- North Billerica MA, US
Mac D. Apodaca - San Jose CA, US
Thomas Michael Trent - Nashua NH, US
James Juen Hsu - Saratoga CA, US
Assignee:
Contour Semiconductor, Inc. - North Billerica MA
International Classification:
H01L 27/04
US Classification:
257 1
Abstract:
The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4Fmemory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

Possible Relatives

David L Trent  Dawn B Trent  Dean M Trent  Dana C Trent  Debra A Trent  Denise M Trent  Danny J Trent  Thomas D Johnson  Thomas Stamps  Thomas W Stancil 

NOTICE: You may not use BackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. BackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.