Timothy M Wegner, 63125 W Main St, Westborough, MA 01581

6687851, Feb 3, 2004

Apr 13, 2000

09/548527

Jeffrey S. Somers - Northborough MA
Mark D. Tetreault - Webster MA
Timothy M. Wegner - Westborough MA

Stratus Technologies Bermuda Ltd. - Hamilton

G06F 1100

714 12, 714 11, 714 13

The inventive system includes an I/O subsystem that controls the synchronization of an off-line CPU to an on-line CPU, such that much of the synchronization operation takes place essentially as a background task for the on-line CPU. The I/O subsystem requests that the on-line CPU provide certain register and memory state information to general purpose registers on an I/O board. The I/O subsystem then provides the register contents to general purpose registers on the off-line CPU board, and the off-line CPU uses the information to set the states of certain of its registers and memory. The I/O system further includes a DMA engine that, at a time set by the I/O subsystem, copies pages of memory from the on-line CPU to the off-line CPU. At the end of the synchronization operation, the off-line CPU is directed to write to a predetermined register on the I/O board. When the off-line CPU performs the write operation, it indicates that the off-line CPU is in a known state and ready to go on-line.

6820213, Nov 16, 2004

Apr 13, 2000

09/548528

Jeffrey S. Somers - Northborough MA
Wen-Yi Huang - Acton MA
Mark D. Tetreault - Webster MA
Timothy M. Wegner - Westborough MA

Stratus Technologies Bermuda, Ltd.

G06F 1100

714 11, 714 45

A fault-tolerant computer system includes first and second central processing units (CPUs) producing essentially identical data output streams, a voter delay buffer having a first FIFO buffer and a second FIFO buffer, and an I/O module connected to the CPUs. The I/O module includes a comparator for bitwise comparing the CPU data output streams. The first CPU data output stream is transmitted to peripheral devices if both CPU outputs remain substantially identical. Otherwise, if the comparator indicates differences, queued first and second CPU data are routed to the first and second FIFOs respectively, and subsequent data are retained in respective CPU buffers. While the CPUs continue processing, ongoing diagnostic procedures attempt to identify one or the other of the CPUs as malfunctioning and the remaining CPU as correctly-functioning. If the resulting diagnosis is inconclusive, the CPU having the lower rate of error correction is identified as being correctly-functioning. In either case, the buffered output and the subsequently processed data output stream from the correctly-functioning CPU are thereafter transmitted to the peripheral devices.

8234521, Jul 31, 2012

Sep 30, 2008

12/242043

Simon Graham - Maynard MA, US
Daniel Lussier - Holliston MA, US
Timothy Wegner - Westborough MA, US
Jeffrey Somers - Northboro MA, US
Steven Haid - Bolton MA, US

Stratus Technologies Bermuda Ltd. - Hamilton

G06F 11/07

714 12, 714 11, 714 10, 714 13

A system is provided for rapidly synchronizing two or more processing elements in a fault-tolerant computing system. Embodiments of this system allow for the rapid synchronization of two processing elements through partial copies of the contents of memory associate with each processing element.