Timothy Brice Heil, 68Lynnwood, WA

7420143, Sep 2, 2008

Oct 12, 2006

11/549101

Douglas Alan Longworth - Brecksville OH, US
Timothy J. Heil - Independence OH, US

Momentive Performance Materials Inc. - Wilton CT

H05B 3/16
C23C 16/00

219543, 219544, 2194441, 2194431, 219540, 219546, 219548, 219553, 392407, 392432, 118725, 118728, 338248, 338249

An article comprising a graphite part coated with a pyrolytic graphite (pG) for increased mechanical strength of at least 25% over an uncoated graphite part. In connector applications for use in a semiconductor processing assembly such as a heater, the pG coated component is overcoated with at least a protective layer of an electrically insulating material, and wherein part of the pG coated graphite part is exposed (uncoated with the protective layer) for providing electrical connections to the assembly.

2014007, Mar 13, 2014

Sep 13, 2012

13/613175

Timothy H. Heil - Sammamish WA, US
Brent F. Hilgart - Rochester MN, US
Andrew D. Hilton - Durham NC, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

G06F 9/38

712240, 712E09051

A branch history table cache is a write cache that stores values of branch history counters written to a branch history table. An update to a branch history table counter is reflected in both the branch history table cache and the branch history table. Before a branch history table counter is updated, a check is made to see if the branch history table counter is in the cache. If not, the branch history table counter is updated based on a value of the branch history table counter that was saved during fetch of the branch history table counter. If, however, the branch history table counter value is in the cache, the value in the cache is used to update the branch history table counter. All branches that use the branch history table counter update the correct counter value, improving processor performance by providing more accurate predictions of branches taken.

2022040, Dec 22, 2022

Jun 22, 2021

17/355114

- Redmond WA, US
Timothy Hume HEIL - Woodinville WA, US
Deepak GOEL - San Jose CA, US

G06F 9/52

Hardware semaphores are utilized to increase the speed with which preconditions are evaluated. On an individual basis, each hardware semaphore can implement a binary semaphore or a counting semaphore. Collections of hardware semaphores can be chained together to implement a chain semaphore that can support multiple conditionals. In addition, hardware semaphores can have the capability, not only of generating an interrupt, but, in addition, being able to generate commands, such as to other semaphores. The implementation of a chain semaphore spanning multiple hardware semaphores can be performed by a compiler at compile time or at run time. An integrated circuit chip can comprise multiple execution units, such as processing cores, and individual ones of the execution units can be associated with multiple hardware semaphores, such as in the form of hardware semaphore arrays. A dedicated network-on-chip enables hardware semaphore communication.

2020023, Jul 23, 2020

Apr 8, 2020

16/843800

- Redmond WA, US
Timothy Hume HEIL - Kirkland WA, US
Amol Ashok AMBARDEKAR - Redmond WA, US
George PETRE - Redmond WA, US
Kent D. CEDOLA - Bellevue WA, US
Larry Marvin WALL - Seattle WA, US
Boris BOBROV - Kirkland WA, US

G06F 13/16
G06N 3/04
G06N 3/063
G06F 12/0862
G06F 9/46
G06F 1/324
G06F 3/06
G06F 9/38
G06F 12/08
G06F 12/10
G06F 15/80
G06F 17/15
G06N 3/06
G06N 3/08
G06N 3/10
H03M 7/30
H04L 12/715
H04L 29/08
G06F 1/3234
G06F 12/02
G06F 13/28

An exemplary computing environment having a DNN module can maintain one or more bandwidth throttling mechanisms. Illustratively, a first throttling mechanism can specify the number of cycles to wait between transactions on a cooperating fabric component (e.g., data bus). Illustratively, a second throttling mechanism can be a transaction count limiter that operatively sets a threshold of a number of transactions to be processed during a given transaction sequence and limits the number of transactions such as multiple transactions in flight to not exceed the set threshold. In an illustrative operation, in executing these two exemplary calculated throttling parameters, the average bandwidth usage and the peak bandwidth usage can be limited. Operatively, with this fabric bandwidth control, the processing units of the DNN are optimized to process data across each transaction cycle resulting in enhanced processing and lower power consumption.

2018029, Oct 18, 2018

Apr 11, 2018

15/950644

- Redmond WA, US
Timothy Hume HEIL - Kirkland WA, US
Amol Ashok AMBARDEKAR - Redmond WA, US
George PETRE - Redmond WA, US
Kent D. CEDOLA - Bellevue WA, US
Larry Marvin WALL - Seattle WA, US
Boris BOBROV - Kirkland WA, US

G06F 1/32
G06N 3/08

An exemplary computing environment having a DNN module can maintain one or more bandwidth throttling mechanisms. Illustratively, a first throttling mechanism can specify the number of cycles to wait between transactions on a cooperating fabric component (e.g., data bus). Illustratively, a second throttling mechanism can be a transaction count limiter that operatively sets a threshold of a number of transactions to be processed during a given transaction sequence and limits the number of transactions such as multiple transactions in flight to not exceed the set threshold. In an illustrative operation, in executing these two exemplary calculated throttling parameters, the average bandwidth usage and the peak bandwidth usage can be limited. Operatively, with this fabric bandwidth control, the processing units of the DNN are optimized to process data across each transaction cycle resulting in enhanced processing and lower power consumption.