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Timothy Mathew Philip, 34107 S Manning Blvd, Albany, NY 12203

Timothy Philip Phones & Addresses

Albany, NY   

Champaign, IL   

Urbana, IL   

2535 Manor Creek Ct, Cumming, GA 30041    678-6431113   

Lilburn, GA   

Mentions for Timothy Mathew Philip

Timothy Philip resumes & CV records

Resumes

Timothy Philip Photo 37

Research Staff Member

Location:
215 south Main Ave, Albany, NY 12203
Industry:
Higher Education
Work:
Lawrence Livermore National Laboratory May 2014 - Aug 2014
Summer Scholar Intern
University of Illinois at Urbana-Champaign May 2014 - Aug 2014
Graduate Research Assistant
Georgia Institute of Technology Jan 2013 - May 2014
Graduate Teaching Assistant
College of Computing at Georgia Tech Aug 2011 - Dec 2012
Senior Teaching Assistant
Freescale Semiconductor May 2012 - Aug 2012
Thin Films Engineer
College of Computing at Georgia Tech Jan 2010 - Aug 2011
Teaching Assistant
Ibm Jan 2010 - Aug 2011
Research Staff Member
Education:
Georgia Institute of Technology 2009 - 2012
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Matlab, C, C++, Python, Latex, Spice, Multisim, Sonnet, Altera Quartus, Photoshop, Dreamweaver, Assembly Language, Simulations, Signal Processing, Statistics, Cvd, Wet Chemical Etching, Photolithography, Fortran
Interests:
Programming
Ultimate
Languages:
English
Malayalam
Latin
Timothy Philip Photo 38

Research Staff Member

Location:
Albany, NY
Work:
Ibm
Research Staff Member
Education:
University of Illinois at Urbana - Champaign 2014 - 2018
Doctorates, Doctor of Philosophy, Philosophy
Timothy Philip Photo 39

Timothy Philip

Publications & IP owners

Us Patents

Multi-Layer Phase Change Memory Device

US Patent:
2022020, Jun 30, 2022
Filed:
Dec 29, 2020
Appl. No.:
17/136384
Inventors:
- Armonk NY, US
Injo Ok - Loudonville NY, US
Jin Ping Han - Yorktown Heights NY, US
Timothy Mathew Philip - Albany NY, US
Nicole Saulnier - Slingerlands NY, US
International Classification:
H01L 45/00
H01L 27/24
G11C 11/54
G11C 13/00
Abstract:
A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.

Phase Change Memory Cell Sidewall Projection Liner

US Patent:
2023009, Mar 30, 2023
Filed:
Sep 29, 2021
Appl. No.:
17/489602
Inventors:
- Armonk NY, US
Timothy Mathew Philip - Albany NY, US
Andrew Herbert Simon - Fishkill NY, US
Matthew T. Shoudy - Guilderland NY, US
Injo Ok - Loudonville NY, US
International Classification:
H01L 45/00
Abstract:
A phase change memory (PCM) cell having a mushroom configuration includes a first electrode, a heater electrically connected to the first electrode, a first projection liner electrically connected to the heater, a PCM material electrically connected to the first projection liner, a second electrode electrically connected to the PCM material, and a second projection liner electrically connected to the first projection liner and the second electrode.

Electrically Insulated Projection Liner For Ai Device

US Patent:
2023008, Mar 16, 2023
Filed:
Sep 13, 2021
Appl. No.:
17/472858
Inventors:
- Armonk NY, US
Timothy Mathew Philip - Albany NY, US
Kevin W. Brew - Niskayuna NY, US
Muthumanickam Sankarapandian - Niskayuna NY, US
Steven Michael McDermott - Wynantskill NY, US
Nicole Saulnier - Slingerlands NY, US
Andrew Herbert Simon - Fishkill NY, US
Sanjay C. Mehta - Niskayuna NY, US
International Classification:
H01L 45/00
Abstract:
A semiconductor structure includes a heater located in a first layer of a device, wherein the heater is surrounded by a dielectric, a phase change memory (PCM) liner in direct contact with a top surface of the heater in a second layer of the device, a spacer disposed adjacent the PCM liner in the second layer of the device, and a PCM stack disposed above the PCM liner in the second layer of the device.

Topological Qubit Device

US Patent:
2021028, Sep 16, 2021
Filed:
Mar 16, 2020
Appl. No.:
16/820048
Inventors:
- Armonk NY, US
Timothy Mathew Philip - Albany NY, US
Sagarika Mukesh - Albany NY, US
Youngseok Kim - Upper Saddle River NJ, US
Devendra K. Sadana - Pleasantville NY, US
Robert Robison - Rexford NY, US
International Classification:
H01L 39/22
H01L 39/02
H01L 39/24
Abstract:
Devices, systems, and/or methods that can facilitate topological quantum computing are provided. According to an embodiment, a device can comprise a circuit layer formed on a wiring layer of the device and that comprises control components. The device can further comprise a topological qubit device formed on the circuit layer and that comprises a nanorod capable of hosting fermions and a quantum well tunable Josephson junction that is coupled to the control components.

Structurally Stable Self-Aligned Subtractive Vias

US Patent:
2021028, Sep 9, 2021
Filed:
Mar 9, 2020
Appl. No.:
16/813682
Inventors:
- Armonk NY, US
Dominik METZLER - Clifton Park NY, US
CHANRO PARK - Clifton Park NY, US
Timothy Mathew Philip - Albany NY, US
International Classification:
H01L 21/768
H01L 21/3213
H01L 23/522
Abstract:
Techniques for forming self-aligned subtractive top vias using a via hardmask supported by scaffolding are provided. In one aspect, a method of forming top vias includes: forming metal lines on a substrate using line hardmasks; patterning vias in the line hardmasks; filling the vias and trenches in between the metal lines with a via hardmask material to form via hardmasks and a scaffolding adjacent to and supporting the via hardmasks; removing the line hardmasks; and recessing the metal lines using the via hardmasks to form the top vias that are self-aligned with the metal lines. The scaffolding can also be placed prior to patterning of the vias in the line hardmasks. A structure formed in accordance with the present techniques containing top vias is also provided.

Patterning Line Cuts Before Line Patterning Using Sacrificial Fill Material

US Patent:
2021021, Jul 8, 2021
Filed:
Jan 7, 2020
Appl. No.:
16/736478
Inventors:
- Armonk NY, US
Timothy Mathew Philip - Albany NY, US
Somnath Ghosh - Clifton Park NY, US
Robert Robison - Rexford NY, US
International Classification:
H01L 21/768
H01L 21/311
H01L 21/033
Abstract:
A method includes forming a dielectric layer on a semiconductor substrate, forming a hard mask layer on the dielectric layer, forming a sacrificial mandrel layer on the hard mask layer, depositing a sacrificial fill material in an opening in the sacrificial mandrel layer and utilizing the sacrificial fill material to selectively pattern the hard mask layer. The pattern defining first and second spaced openings in the hard mask layer. The method further includes etching the dielectric layer through the first and second openings in the hard mask layer to create first and second trenches in the dielectric layer separated by a dielectric segment of the dielectric layer.

Phase Change Memory Device

US Patent:
2021013, May 6, 2021
Filed:
Nov 1, 2019
Appl. No.:
16/671748
Inventors:
- Armonk NY, US
Kevin W. Brew - Albany NY, US
Timothy M. Philip - Albany NY, US
Muthumanickam Sankarapandian - Niskayuna NY, US
Sanjay C. Mehta - Niskayuna NY, US
Nicole Saulnier - Slingerlands NY, US
Steven M. Mcdermott - Wynantskill NY, US
International Classification:
H01L 45/00
G11C 13/00
Abstract:
A phase change material memory device is provided. The phase change material memory device includes one or more electrical contacts in a substrate, and a dielectric cover layer on the electrical contacts and substrate. The phase change material memory device further includes a lower conductive shell in a trench above one of the one or more electrical contacts, and an upper conductive shell on the lower conductive shell in the trench. The phase change material memory device further includes a conductive plug filling the upper conductive shell. The phase change material memory device further includes a liner layer on the dielectric cover layer and conductive plug, and a phase change material block on the liner layer on the dielectric cover layer and in the trench.

Selective Patterning Of Vias With Hardmasks

US Patent:
2021008, Mar 18, 2021
Filed:
Sep 13, 2019
Appl. No.:
16/570059
Inventors:
- Armonk NY, US
Ashim Dutta - Menands NY, US
Dominik Metzler - Saratoga Springs NY, US
Timothy M. Philip - Albany NY, US
Sagarika Mukesh - Albany NY, US
International Classification:
H01L 21/768
H01L 21/033
H01L 23/522
Abstract:
Methods and structures for forming vias are provided. The method includes forming a structure that includes an odd line hardmask and an even line hardmask. The odd line hardmask and the even line hardmask include different hardmask materials that have different etch selectivity with respect to each other. The method includes patterning vias separately into the odd line hardmask and the even line hardmask based on the different etch selectivity of the different hardmask materials. The method also includes forming via plugs at the vias. The method includes cutting even line cuts and odd line cuts into the structure. The even line cuts and the odd line cuts are self-aligned with the vias. The vias are formed at line ends of the structure.

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