Tomas Palacios resumes & CV records
Resumes
Tomas Alvarez Palacios
Tomas M PalaciosLeavenworth, KS
Tomas Palacios Phones & Addresses
Leavenworth, KS
98 Nichols St, Everett, MA 02149 617-3811847
21 B St, Everett, MA 02149 617-3890748
Mentions for Tomas M Palacios
Publications & IP owners
Us Patents
Methods To Shape The Electric Field In Electron Devices, Passivate Dislocations And Point Defects, And Enhance The Luminescence Efficiency Of Optical Devices
US Patent:
8114717, Feb 14, 2012
Filed:
Nov 15, 2006
Appl. No.:
11/599874
Inventors:
Tomas Palacios - Cambridge MA, US
Likun Shen - Goleta CA, US
Umesh K. Mishra - Montecito CA, US
Likun Shen - Goleta CA, US
Umesh K. Mishra - Montecito CA, US
Assignee:
The Regents of the University of California - Oakland CA
International Classification:
H01L 21/335
US Classification:
438142, 438167, 438172, 257192, 257194, 257E21403, 257E21407
Abstract:
A fluorine treatment that can shape the electric field profile in electronic devices in 1, 2, or 3 dimensions is disclosed. A method to increase the breakdown voltage of AlGaN/GaN high electron mobility transistors, by the introduction of a controlled amount of dispersion into the device, is also disclosed. This dispersion is large enough to reduce the peak electric field in the channel, but low enough in order not to cause a significant decrease in the output power of the device. In this design, the whole transistor is passivated against dispersion with the exception of a small region 50 to 100 nm wide right next to the drain side of the gate. In that region, surface traps cause limited amounts of dispersion, that will spread the high electric field under the gate edge, therefore increasing the breakdown voltage. Three different methods to introduce dispersion in the 50 nm closest to the gate are described: (1) introduction of a small gap between the passivation and the gate metal, (2) gradually reducing the thickness of the passivation, and (3) gradually reducing the thickness of the AlGaN cap layer in the region close the gate.
Devices Based On Si/Nitride Structures
US Patent:
8188459, May 29, 2012
Filed:
Oct 13, 2009
Appl. No.:
12/577892
Inventors:
Tomas Palacios - Cambridge MA, US
Jinwook Chung - Cambridge MA, US
Jinwook Chung - Cambridge MA, US
Assignee:
Massachusetts Institute of Technology - Cambridge MA
International Classification:
H01L 29/06
H01L 31/0328
H01L 31/0336
H01L 31/072
H01L 31/109
H01L 31/0328
H01L 31/0336
H01L 31/072
H01L 31/109
US Classification:
257 20, 257 24, 257192, 257E29229
Abstract:
A nitride-based semiconductor device is provided. The nitride-base semiconductor device includes a substrate comprising one or more locally etched regions and a buffer layer comprising one or multiple InAlGaN layers on the substrate. A channel layer includes GaN on the buffer layer. A barrier layer includes one or multiple AlGaN layers on the channel layer.
Dual-Gate Normally-Off Nitride Transistors
US Patent:
8587031, Nov 19, 2013
Filed:
Jul 25, 2012
Appl. No.:
13/557414
Inventors:
Bin Lu - Cambridge MA, US
Tomas Palacios - Cambridge MA, US
Tomas Palacios - Cambridge MA, US
Assignee:
Massachusetts Institute of Technology - Cambridge MA
International Classification:
H01L 29/66
US Classification:
257194, 257 76, 257E21407, 257E29264, 438172
Abstract:
A dual-gate normally-off nitride transistor that includes a first gate structure formed between a source electrode and a drain electrode for controlling a normally-off channel region of the dual-gate normally-off nitride transistor. A second gate structure is formed between the first gate structure and the drain electrode for modulating a normally-on channel region underneath the second gate structure. The magnitude of the threshold voltage of the second gate structure is smaller than the drain breakdown of the first gate structure for proper operation of the dual-gate normally-off nitride transistor.
Enhancement-Mode Nitride Transistor
US Patent:
2010008, Apr 8, 2010
Filed:
Oct 6, 2009
Appl. No.:
12/574146
Inventors:
Bin Lu - Cambridge MA, US
Tomas Palacios - Cambridge MA, US
Tomas Palacios - Cambridge MA, US
International Classification:
H01L 29/778
H01L 21/335
H01L 21/335
US Classification:
257194, 438172, 257E29246, 257E21403
Abstract:
A heterojunction for use in a transistor structure is provided. The heterojunction includes a barrier layer positioned beneath a gate region of the transistor structure. The barrier layer includes nitride-based semiconductor materials. A channel layer provides electrical conduction An intermediate layer near the barrier layer and including nitride-based semiconductor materials having a wider bandgap than the channel layer
Wafer Bonding Technique In Nitride Semiconductors
US Patent:
2010030, Dec 2, 2010
Filed:
Jun 1, 2009
Appl. No.:
12/475740
Inventors:
Jinwook Chung - Cambridge MA, US
Han Wang - Cambridge MA, US
Tomas Palacios - Cambridge MA, US
Han Wang - Cambridge MA, US
Tomas Palacios - Cambridge MA, US
International Classification:
H01L 29/20
H01L 21/18
H01L 21/18
US Classification:
257 76, 438455, 257201, 257194, 257E29089, 257E21087
Abstract:
A semiconductor arrangement is provided that includes one or more substrate structures. One or more nitride-based material structures are used in fabricating nitride-based devices. One or more intermediary layers are interposed between the one or more substrate structures and the one or more nitride-based material structures. The one or more intermediary layers support the lattice mismatch and thermal expansion coefficients between the one or more nitride-based material structure and the one or more substrate structures. Several new electronic devices based on this arrangement are described.
Performance Of Nitride Semiconductor Devices
US Patent:
2012001, Jan 19, 2012
Filed:
Jun 23, 2011
Appl. No.:
13/167236
Inventors:
Tomas Apostol Palacios - Cambridge MA, US
Jinwook Chung - Los Angeles CA, US
Jinwook Chung - Los Angeles CA, US
Assignee:
Massachusetts Institute of Technology - Cambridge MA
International Classification:
H01L 29/778
H01L 21/20
H01L 29/772
H01L 21/28
H01L 21/20
H01L 29/772
H01L 21/28
US Classification:
257194, 438585, 438478, 257288, 257192, 257E2119, 257E2109, 257E29246, 257E29242
Abstract:
A method of forming a transistor over a nitride semiconductor layer includes surface-treating a first region of a nitride semiconductor layer and forming a gate over the first region. Surface-treating the first region can cause the transistor to have a higher intrinsic small signal transconductance than a similar transistor formed without the surface treatment. A portion of the bottom of the gate can be selectively etched. A resulting transistor can include a nitride semiconductor layer having a surface-treated region and a gate formed over or adjacent to the surface-treated region.
Control Of Current Collapse In Thin Patterned Gan
US Patent:
2020002, Jan 23, 2020
Filed:
Dec 13, 2018
Appl. No.:
16/219300
Inventors:
- Armonk NY, US
- Cambridge MA, US
Tomas Palacios - Belmont MA, US
Daniel Piedra - Cambridge MA, US
Devendra K. Sadana - Pleasantville NY, US
- Cambridge MA, US
Tomas Palacios - Belmont MA, US
Daniel Piedra - Cambridge MA, US
Devendra K. Sadana - Pleasantville NY, US
International Classification:
H01L 21/306
H01L 21/02
H01L 21/02
Abstract:
A GaN device is formed on a semiconductor substrate having a plurality of recessed regions formed in a surface thereof. A seed layer, optional buffer layer, and gallium nitride layer such as a carbon-doped gallium nitride layer are successively deposited within the recessed regions. Improved current collapse response of the GaN device is attributed to maximum length and width dimensions of the multilayer stack.
Ultrasensitive Thermo-Mechanical Bolometer
US Patent:
2019039, Dec 26, 2019
Filed:
Jun 23, 2019
Appl. No.:
16/449410
Inventors:
- Cambridge MA, US
Xiang Ji - Cambridge MA, US
Tomas Palacios - Belmont MA, US
Jing Kong - Winchester MA, US
Xiang Ji - Cambridge MA, US
Tomas Palacios - Belmont MA, US
Jing Kong - Winchester MA, US
Assignee:
Massachusetts Institute of Technology - Cambridge MA
International Classification:
G01B 7/16
G01J 5/20
F16K 31/00
G01J 5/20
F16K 31/00
Abstract:
A thermo-mechanical bolometer includes a substrate and a sensing component mounted on the substrate. The sensing element comprises (a) at least one thermal-actuation component mounted in parallel with the substrate and (b) a strain sensor mounted on the at least one layer of thermal-actuation component. The at least one thermal-actuation component alone or in combination (a) absorbs electromagnetic waves and converts energy from absorbed electromagnetic waves into a change in temperature and (b) converts the change in temperature into a deformation of the at least one layer. The strain sensor comprises a layer of fragments with a gap space between the fragments, wherein the strain sensor senses the deformation or mechanical movement and exhibits a change in electrical resistance in response to the sensed deformation or mechanical movement.
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