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Varun Kumar Singh, 429861 Valley Ranch Pkwy W UNIT 2081, Irving, TX 75063

Known as:
Varun K Singh Varun Kumar
Related to:
Vipin K Agnihotri

Varun Singh Phones & Addresses

Irving, TX   

Alpharetta, GA   

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Varun Singh resumes & CV records

Resumes

Varun Singh Photo 45

Varun Singh - Lexington, MA

Work:
WELLINGTON MANAGEMENT COMPANY, LLP Feb 2005 to Present
Vice President (Equity Analyst) ROBERT W. BAIRD & CO - Milwaukee, WI Jul 2003 to Feb 2005
Equity Analyst, Baird Investment Management WELLINGTON MANAGEMENT COMPANY, LLP - Boston, MA Jun 2002 to Sep 2002
Equity Analyst (Intern) DALLAS SEMICONDUCTOR CORP - Dallas, TX Jun 1997 to Aug 2001
Senior R&D Engineer, Advanced Technology Group TEXAS INSTRUMENTS, INC - Dallas, TX Jun 1996 to Sep 1996
Research Intern, Multi-layered Interconnects Group
Education:
UNIVERSITY OF CHICAGO, GRADUATE SCHOOL OF BUSINESS - Chicago, IL Sep 2001 to Jun 2003
Master of Business Administration in Finance and Strategy STATE UNIVERSITY OF NEW YORK - Stony Brook, NY Sep 1992 to May 1997
Ph.D. in Materials Science and Engineering INDIAN INSTITUTE OF TECHNOLOGY - Mumbai, Maharashtra
Varun Singh Photo 46

Varun Singh - US

Publications & IP owners

Us Patents

Polysilicon Resistor Having Adjustable Temperature Coefficients And The Method Of Making The Same

US Patent:
2002000, Jan 24, 2002
Filed:
Sep 26, 2001
Appl. No.:
09/964192
Inventors:
Varun Singh - Dallas TX, US
Tanmay Kumar - Denton TX, US
Thomas Harrington - Carrollton TX, US
Roy Hensley - Plano TX, US
Allan Mitchell - Heath TX, US
Jack Qian - Plano TX, US
Assignee:
Dallas Semiconductor Corporation
International Classification:
H01L029/00
US Classification:
257/538000
Abstract:
A polysilicon resistor is formed using a late implant process. Low dopant concentrations on the order of 6×10to 3.75×10have shown good results. with a reduced post anneal temperature. Both the first and second order temperature coefficients (TC1 and TC2) can then be adjusted. Using electrical trimming resistors can be produced with highly linear temperature characteristics. By varying the geometries of the resistors, low trimming threshold current densities and voltages can be used to produce good results.

Method Of Making Polysilicon Resistor Having Adjustable Temperature Coefficients

US Patent:
6306718, Oct 23, 2001
Filed:
Apr 26, 2000
Appl. No.:
9/558905
Inventors:
Varun Singh - Dallas TX
Tanmay Kumar - Denton TX
Thomas E. Harrington - Carrollton TX
Roy Austin Hensley - Plano TX
Allan T. Mitchell - Heath TX
Jack Gang Qian - Plano TX
Assignee:
Dallas Semiconductor Corporation - Dallas TX
International Classification:
H01L 2702
US Classification:
438382
Abstract:
A polysilicon resistor is formed using a late implant process. Low dopant concentrations on the order of 6. times. 10. sup. 19 to 3. 75. times. 10. sup. 20 have shown good results. with a reduced post anneal temperature. Both the first and second order temperature coefficients (TC1 and TC2) can then be adjusted. Using electrical trimming resistors can be produced with highly linear temperature characteristics. By varying the geometries of the resistors, low trimming threshold current densities and voltages can be used to produce good results.

Management Of Multiple Memory In-Field Self-Repair Options

US Patent:
2022031, Oct 6, 2022
Filed:
Jun 17, 2022
Appl. No.:
17/843897
Inventors:
- Dallas TX, US
Varun SINGH - Plano TX, US
International Classification:
G11C 29/44
G11C 29/42
G11C 29/14
G11C 17/16
Abstract:
A system includes a processor and a memory set coupled to the processor. The system also includes a repair circuit coupled to the memory set. The repair circuit includes a first repair circuit and a second repair circuit. The repair circuit also includes a test controller configured to select between the first repair circuit and the second repair circuit to perform an in-field self-repair of the memory set.

Non-Volatile Memory Compression For Memory Repair

US Patent:
2022019, Jun 23, 2022
Filed:
Dec 17, 2020
Appl. No.:
17/125244
Inventors:
- Dallas TX, US
RAMAKRISHNAN VENKATASUBRAMANIAN - PLANO TX, US
VARUN SINGH - PLANO TX, US
International Classification:
G06F 11/14
H03M 7/30
Abstract:
One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.

Built-In Memory Repair With Repair Code Compression

US Patent:
2022019, Jun 23, 2022
Filed:
Dec 17, 2020
Appl. No.:
17/125323
Inventors:
- Dallas TX, US
VARUN SINGH - PLANO TX, US
International Classification:
G11C 29/44
G11C 29/40
G11C 29/16
Abstract:
In a described example, an integrated circuit (IC) includes a repairable memory system. A repair controller is coupled to the repairable memory system. The repair controller includes compression logic configured to encode memory repair code data for a respective instance of the repairable memory system and provide compressed repair data. A non-volatile memory controller is coupled to the repair controller and to non-volatile memory. The non-volatile memory controller is configured to transfer the compressed repair data to the non-volatile memory for storage.

Management Of Multiple Memory In-Field Self-Repair Options

US Patent:
2020032, Oct 8, 2020
Filed:
Aug 13, 2019
Appl. No.:
16/539805
Inventors:
- Dallas TX, US
Varun SINGH - Plano TX, US
International Classification:
G11C 29/44
G11C 29/14
G11C 29/42
G11C 17/16
Abstract:
A system includes a processor and a memory set coupled to the processor. The system also includes a repair circuit coupled to the memory set. The repair circuit includes a first repair circuit and a second repair circuit. The repair circuit also includes a test controller configured to select between the first repair circuit and the second repair circuit to perform an in-field self-repair of the memory set.

Possible Relatives

David J Singh  Davinder Singh  Davinderpal Singh  Dawinder Singh  Dale D Singh  Daler Singh  Dalip D Singh  Varun Patel  Varun Kohli  Varun Sehgal 

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