Vijendra Pal Singh, 8913179 Shadow Mountain Dr, Saratoga, CA 95070

4584681, Apr 22, 1986

Sep 2, 1983

6/528769

Shanker Singh - Fishkill NY
Vijendra P. Singh - Saratoga CA

International Business Machines Corporation - Armonk NY

G01R 3128
G06F 1110

371 10

Spare chips are employed together with a replacement algorithm to replace chips in memory array when failure is generally more extensive then unrelated cell fails in the memory chips. That is, substitution will be made if an error condition is a result of the failure of a whole chip (chip-kill), a segment of a chip (island-kill), a column of bits of a chip or a row of bits of a chip but will not be performed when it is due to a single failed cell. The replacement of a chip with a chip-kill or with an island-kill is done on the fly and involves only a row of the memory chips or elements leaving other elements of the memory unaffected by the replacement.

5621665, Apr 15, 1997

Aug 31, 1994

8/299462

Saki P. Ghosh - San Jose CA
Vijendra P. Singh - Saratoga CA

International Business Machines Corporation - Armonk NY

G05B 1300

364552

A method is provided for defining a minimally sized set of industrial process experiments which are sufficient to identify optimal levels for factors which go into the process. The method defines levels for the factors for the experiments in terms of a symmetric orthogonal array, which represents a valid Galois field for a number of levels for each factor equal to a prime number. The factors are divided into first and second groups. In accordance with Galois field theory, the required number of experiments is a number sufficient to provide a complete set of permutations of levels for the first group of factors. For each experiment, the levels for the second group of factors are determined based on the levels of the first group of factors. In a preferred embodiment, level symbols which are consecutive integers ranging upward from zero are assigned to the levels for each factor. The levels for the second group of factors are computed by performing a modulo addition of the levels for the first factors, scaled by coefficients which differ for the different experiments.

4534029, Aug 6, 1985

Mar 24, 1983

6/478594

Shanker Singh - Fishkill NY
Vijendra P. Singh - San Jose CA

International Business Machines Corporation - Armonk NY

G11C 1140
G06F 1104

371 10

This permutation circuit can be considered to be a multi-bit adder without a carry. In one embodiment it takes the form of m address bits being fed to m+y 2-way exclusive OR gates with m+y permutation bits to generate m+y input bits accessing a decoder with 2. sup. m output positions. In another embodiment the decoder takes the form an m bit adder with which adds m address bits to m permutation bits to generate m bit actual address. Multiple decoders of both types may be joined together in various combinations to generate higher order addresses. Also, k full-adder of less than m bits can also be used in similar fashion as m+y Exor gates to provide shift rotate capability within a desired block of 2. sup. y rows.

4584682, Apr 22, 1986

Sep 2, 1983

6/528718

Siddharth R. Shah - Hopewell Junction NY
Shanker Singh - Fishkill NY
Vijendra P. Singh - Saratoga CA

International Business Machines Corporation - Armonk NY

G11C 1300

371 10

An array substitution scheme is used to substitute a spare chip for a faulty chip when a UE condition results from an alignment of two errors in bit positions accessed through the same decoder while the bit permutation apparatus is used to misalign fault bits when they occur in bit positions accessed through different decoders.