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Vincent L Mcneil, 57Phoenix, AZ

Known as:
Vincent Leon Mcneil Vince L Mcneil Vincent L Mcneal Vicent Mcneil Vincent Mcniel Mcneil Vicent

Vincent Mcneil Phones & Addresses

Phoenix, AZ   

Tempe, AZ   

The Colony, TX   

Boerne, TX   

Flagstaff, AZ   

Jay, OK   

Batesville, AR   

Work

Company: Tyler isd 2014 Position: Student teacher

Education

School / High School: Texas College Tyler- Tyler, TX 2013
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Vincent Mcneil resumes & CV records

Resumes

Vincent Mcneil Photo 37

Product Line Manager, Powertrain Drivers And Idc, Drivers And Energy Business Unit

Location:
Phoenix, AZ
Industry:
Semiconductors
Work:
Freescale Semiconductor
Product Line Manager, Powertrain Drivers and Idc, Drivers and Energy Business Unit Freescale Semiconductor May 2013 - Sep 2014
Product Line Manager, Bldc Gate Drivers and Idc, Safety Systems Bu Texas Instruments Mar 2009 - Apr 2013
Systems Engineering and Marketing, Signal Chain Team, Hpa Texas Instruments Oct 2007 - Mar 2009
Product Line Manager, Wireless Connectivity, Medical Bu Texas Instruments Mar 2007 - Oct 2007
Manager, Systems and Applications, Medical Bu Texas Instruments Feb 2005 - Mar 2007
Manager, Advanced Architecture and Chip Technology Team Texas Instruments Mar 2004 - Feb 2005
Senior Technologist, Advanced Architecture and Chip Technology Team Texas Instruments Feb 2002 - Mar 2004
Business Manager, Dces Video and Imaging Bu Texas Instruments May 2001 - Feb 2002
Japan Manager, Imaging Business Unit Texas Instruments Jun 1994 - May 2001
Various, Manager Network Camera Bu, Manager Broadband Systems Eng., Ethernet Apps Engineer Cmos Integ Engineer
Education:
Massachusetts Institute of Technology 1988 - 1994
Doctorates, Doctor of Philosophy, Electrical Engineering Tokyo Institute of Technology 1988 - 1988
Massachusetts Institute of Technology 1985 - 1988
Master of Science, Masters, Electrical Engineering Massachusetts Institute of Technology 1981 - 1985
Bachelors, Bachelor of Science, Electrical Engineering, Computer Science
Skills:
Semiconductors, Ic, Analog, Mixed Signal, Soc, Product Development, Cmos, Wireless, Power Management, Competitive Analysis, Product Marketing, Eda, Systems Engineering, Rf, Digital Signal Processors, Electrical Engineering, New Business Development, Embedded Systems, Consumer Electronics, Electronics, Contract Negotiation, Engineering Management, Marketing Communications, Medical Devices, Energy Harvesting, Applications Engineering, Circuit Design, Start Ups, System on A Chip
Languages:
Japanese
Vincent Mcneil Photo 38

Vincent Mcneil

Location:
Phoenix, AZ
Work:
University of Maryland
Student
Education:
University of Maryland
Vincent Mcneil Photo 39

Customer Service

Location:
Phoenix, AZ
Industry:
Consumer Services
Work:
Vince
Customer Service
Vincent Mcneil Photo 40

Vincent Mcneil

Vincent Mcneil Photo 41

Vincent Mcneil

Vincent Mcneil Photo 42

Vincent Mcneil

Skills:
Management
Vincent Mcneil Photo 43

Vincent Mcneil

Vincent Mcneil Photo 44

Vincent Mcneil - Dallas, TX

Work:
Tyler ISD 2014 to 2000
Student Teacher Franklin D. Roosevelt High School - Dallas, TX 2007 to 2008
Basketball & Football Captain Franklin D. Roosevelt High School - Dallas, TX 2006 to 2008
Newspaper Representative Franklin D. Roosevelt High School - Dallas, TX 2006 to 2007
Junior Class President

Publications & IP owners

Us Patents

Method To Enhance The Formation Of Nucleation Sites On Silicon Structures And An Improved Silicon Structure

US Patent:
6429455, Aug 6, 2002
Filed:
Sep 16, 1999
Appl. No.:
09/397462
Inventors:
Vincent Maurice McNeil - Dallas TX
Jorge Adrian Kittl - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2904
US Classification:
257 49, 257763, 257764, 257770, 257384, 257388, 257412, 438583, 438649, 438655, 438685, 438683
Abstract:
A method to enhance the formation of nucleation sites on at least one narrow silicon structure comprises the step: forming at least one nucleation region ( ): masking the at least one narrow silicon structure ( ) with a mask ( ); treating the at least one nucleation region ( ) to enhance an ability of said region to form C54 nucleation sites; and removing the mask from the at least one narrow silicon structure ( ). In another embodiment, a silicon device capable of undergoing a phase transformation comprises at least one narrow silicon structure ( ) formed of TiSi ; and at least one nucleation region ( ) attached to the at least one narrow silicon region ( ), said at least one nucleation region ( ) having a width which is greater than a width of said at least one narrow silicon structure ( ) and said at least one nucleation region ( ) capable of generating a high density of C54 nucleation sites such that said high density of nucleation sites causes a phase transformation ( ) to propagate along the at least one silicon structure ( ).

Method For Designing Shallow Junction, Salicided Nmos Transistors With Decreased Electrostatic Discharge Sensitivity

US Patent:
5793083, Aug 11, 1998
Filed:
Nov 25, 1996
Appl. No.:
8/755924
Inventors:
E. Ajith Amerasekera - Plano TX
Vincent M. McNeil - Dallas TX
Mark S. Rodder - University Park TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2362
US Classification:
257355
Abstract:
A technique for providing a design window for scaled technologies in which good electrostatic discharge/electrical over stress damage and optimum transistor operation can be achieved without the use of additional masks or design steps. The M, beta, and R. sub. sub parameters of the NMOS transistor 13 and associated parasitic npn transistor 10 are selected to provide the design window.

Method To Enhance The Formation Of Nucleation Sites On Silicon Structures And An Improved Silicon Structure

US Patent:
6242333, Jun 5, 2001
Filed:
Jan 5, 1999
Appl. No.:
9/225881
Inventors:
Vincent Maurice McNeil - Dallas TX
Jorge Adrian Kittl - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 213205
H01L 214763
H01L 21425
H01L 2144
US Classification:
438592
Abstract:
A method to enhance the formation of nucleation sites on at least one narrow silicon structure comprises the steps: forming at least one nucleation region (206/208); masking the at least one narrow silicon structure (202) with a mask (302); treating the at least one nucleation region (206/208) to enhance an ability of said region to form C54 nucleation sites; and removing the mask from the at least one narrow silicon structure (202). In another embodiment, a semiconductor device capable of undergoing a phase transformation comprises at least one narrow silicon structure (202) formed of TiSi. sub. 2 ; and at least one nucleation region (206/208) attached to the at least one narrow silicon structure (202), said at least one nucleation region (206/208) having a width which is greater than a width of said at least one narrow silicon structure (202) and said at least one nucleation region (206/208) capable of generating a high density of C54 nucleation sites such that said high density of nucleation sites causes a phase transformation (502a/502b) to propagate along the at least one silicon structure (202).

Selective Area Halogen Doping To Achieve Dual Gate Oxide Thickness On A Wafer

US Patent:
6093659, Jul 25, 2000
Filed:
Mar 25, 1998
Appl. No.:
9/047713
Inventors:
Douglas T. Grider - McKinney TX
Vincent M. McNeil - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2137
H01L 21469
US Classification:
438758
Abstract:
A method for forming an integrated circuit having multiple gate oxide thicknesses is disclosed herein. The circuit (10) is processed up to gate oxide formation. A pattern (36) is then formed exposing areas of the circuit where a thinner gate oxide (20) is desired. These areas are then implanted with a halogen species such as fluorine or chlorine, to retard oxidation. The pattern (36) is then removed and an oxidation step is performed. Oxidation is selectively retarded in areas (14) previously doped with the halogen species but not in the remaining areas (12). Thus, a single oxidation step may be used to form gate oxides (20,22) of different thicknesses.

Possible Relatives

David E Mcneil  Dawn C Mcneil  Deanna C Mcneil  Damon L Mcneil  Deborah E Mcneil  Daniel Mcneil  Demetria M Mcneil  Vincent R Stanbro  Vincent Johnston 

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