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Vincent Chiang Shih, 499651 E Lemon Ave, Arcadia, CA 91007

Known as:
Vincent C Shih Shih Chaing Choungyaw Yaw Shieh Shih Chiang Chian G Shih Choung Yaw Shieh Chaing Shih Chiang Shih Yaw Shieh Choungyaw
Related to:
John C Wu 87

Vincent Shih Phones & Addresses

Baldwin Park, CA   

Arcadia, CA   

Monterey Park, CA   

Palo Alto, CA   

Los Altos, CA   

San Jose, CA   

Pleasanton, CA   

Baldwin Park, CA   

Morrisville, NC   

La Puente, CA   

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Vincent Shih resumes & CV records

Resumes

Vincent Shih Photo 25

Director Of Finance

Position:
Director of Finance at Don Bosco Technical Institute, Administrator at Los Angeles International Church of Christ
Location:
Greater Los Angeles Area
Industry:
Education Management
Work:
Don Bosco Technical Institute since Jul 2010
Director of Finance Los Angeles International Church of Christ since Jan 2000
Administrator
Education:
University of California, Irvine - The Paul Merage School of Business 2005 - 2007
MBA, Accounting, Finance University of California, Los Angeles 1993 - 1999
BA, History
Skills:
Excel, PowerPoint, Microsoft Office 2007, Blackbaud, 10 Key, Endowments, Budget Preparation, Financial Management, Financial Modeling, Financial Analysis, Microsoft Excel, Accounting, Managerial Finance, Cash Management, Budgets, Financial Accounting, Finance, Analysis, Customer Service, Accounts Payable, Nonprofits, Public Speaking, Leadership, Asset Management, Due Diligence, Strategic Planning, Microsoft Office, Project Management, Investments
Vincent Shih Photo 26

Vincent Shih

Location:
Aiken, South Carolina
Industry:
Defense & Space
Skills:
Engineering Management, Process Safety, Nuclear Safety, Regulatory Requirements, Technical Presentations, Written & Oral Presentation Skills

Publications & IP owners

Us Patents

Interconnects Containing Serpentine Line Structures For Three-Dimensional Memory Devices And Methods Of Making The Same

US Patent:
2019025, Aug 22, 2019
Filed:
Feb 17, 2018
Appl. No.:
15/898544
Inventors:
- PLANO TX, US
Chenche Huang - Campbell CA, US
Chun-Ming Wang - Fremont CA, US
Vincent Shih - San Jose CA, US
International Classification:
H01L 23/528
H01L 23/522
H01L 27/24
H01L 27/11556
H01L 27/11582
H01L 21/768
Abstract:
A device structure includes an array of semiconductor devices located in an array region over a substrate, metal lines laterally extending from the device region to a peripheral interconnection region, and interconnect via structures located in the peripheral interconnection region, and contacting a portion of a respective one of the plurality of metal lines. The metal lines include a first metal line and a second metal line each having a serpentine region which contacts a respective interconnect via structure.

Air Gap Three-Dimensional Cross Rail Memory Device And Method Of Making Thereof

US Patent:
2019025, Aug 22, 2019
Filed:
Feb 17, 2018
Appl. No.:
15/898571
Inventors:
- Plano TX, US
Satoru MAYUZUMI - Yokkaichi, JP
Vincent SHIH - San Jose CA, US
International Classification:
H01L 27/11556
H01L 27/102
H01L 27/06
H01L 21/822
G11C 16/04
H01L 45/00
Abstract:
A memory device includes first conductive rails laterally extending along a first horizontal direction over a substrate, a rectangular array of first memory pillar structures, each containing a memory element, overlying top surfaces of the first conductive rails, second conductive rails laterally extending along a second horizontal direction and overlying top surfaces of the rectangular array of first memory pillar structures, and a one-dimensional array of first cavities free of solid material portions therein, laterally extending along the second horizontal direction and located between neighboring pairs of the second conductive rails.

Three-Dimensional Reram Memory Device Employing Replacement Word Lines And Methods Of Making The Same

US Patent:
2019000, Jan 3, 2019
Filed:
Jun 28, 2017
Appl. No.:
15/635321
Inventors:
- Plano TX, US
Mitsuteru MUSHIGA - Yokkaichi, JP
Vincent SHIH - San Jose CA, US
Akio NISHIDA - Yokkaichi, JP
Tuan PHAM - San Jose CA, US
International Classification:
H01L 27/24
H01L 45/00
H01L 23/522
H01L 23/528
Abstract:
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, resistive memory elements located in the alternating stack in first and second array regions and contact via structures located in a contact region between the first and the second array regions. The contact via structures have different depths and contact different electrically conductive layers. Support pillars are located in the contact region and extending through the alternating stack. At least one conduction channel area is located between the contact via structures in the contact region. The conduction channel area contains no support pillars, and all electrically conductive layers in the conduction channel area are continuous from the first array region to the second array region.

Possible Relatives

David Y Shih  Diana Shih  Edward T Shih  Elena Shih  Emily Shih  Eric N Shih  Eve K Shih  Vincent G Johnson  Vincent R Stanbro  Vincent Johnston 

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