Vinod K Sharma, 36New Hyde Park, NY

6446517, Sep 10, 2002

Nov 20, 2000

09/717456

Vinod Sharma - Los Gatos CA
Debasis Baral - San Jose CA

Samsung Electronics Company

G01N 1700

738656

An environmental chamber that can be used to test a device under test such as a hard disk drive. The environmental chamber may include an electronically controlled shutter that controls the flow of controlled particles from a second chamber to a first chamber. The controlled particles flow to a device under the test located within the first chamber. The shutter can be closed when a predetermined threshold of contaminants is detected by the environmental chamber. This two-chamber method provides a stable and uniform density of particle environment around the drive.

6564328, May 13, 2003

Dec 23, 1999

09/471795

Edward T. Grochowski - San Jose CA
Vinod Sharma - Sunnyvale CA
Gregory S. Matthews - Santa Clara CA
Vivek Joshi - Sunnyvale CA
Ralph M. Kling - Sunnyvale CA

Intel Corporation - Santa Clara CA

G06F 126

713320

The present invention provides a digital-based mechanism for adjusting the power consumption in an integrated digital circuit such as a processor. The processor includes one or more functional units and a digital throttle that monitors activity states of the processors functional units to estimate the processors power consumption. One embodiment of the digital throttle includes one or more gate units, a monitor circuit, and a throttle circuit. Each gate unit controls the delivery of power delivery to a functional unit of the processor and provides a signal that indicates the activity state of its associated functional unit. The monitor circuit determines an estimated power consumption level from the signals and compares the estimated power consumption with a threshold power level. The throttle circuit adjusts the instruction flow in the processor if the estimated power consumption level exceeds the threshold power level.

6591341, Jul 8, 2003

Mar 31, 2000

09/540754

Vinod Sharma - San Jose CA

Intel Corporation - Santa Clara CA

G06F 1200

711122, 711124, 711144, 711146, 711156

A multilevel cache system and method. A first data array and a second data array are coupled to a merged tag array. The merged tag array stores tags for both the first data array and second data array.

6609209, Aug 19, 2003

Dec 29, 1999

09/474461

Vivek Tiwari - Santa Clara CA
Vinod Sharma - San Jose CA
Sivakumar Makineni - Sunnyvale CA
Suri B. Medapati - San Jose CA

Intel Corporation - Santa Clara CA

G06F 132

713322

A processor includes a pipeline having first and second stages and a shift register having first and second latches. An interface circuit is used to provide a clock signal from a clock signal line to the first and second stages based, at least in part, on first and second bits to be stored in the first and second latches, respectively.

6747843, Jun 8, 2004

Mar 26, 2002

10/107387

Vinod Sharma - Los Gatos CA
Joseph Chang - Cupertino CA
Hyung Jai Lee - San Jose CA

Samsung Electronics Co., LTD - Suwon

G11B 554

360128, 3602544

The invention includes a method of A wipping part of the load ramp is a convex finger crossing the read-write head path of motion with respect to a lifting tab engagably moving across the loading ramp.

6763368, Jul 13, 2004

Dec 22, 2000

09/746940

Bharat Bhushan - Cupertino CA
Vinod Sharma - Sunnyvale CA
Edward Grochowski - San Jose CA
John Crawford - Saratoga CA

Intel Corporation - Santa Clara CA

G06F 704

708671, 708200

A method and apparatus for adding numbers represented in redundant form or for subtracting numbers received in redundant form and for comparing results in redundant form for equality to an expected value. A redundant arithmetic circuit performs an arithmetic operation on operands received in redundant form to generate a result represented in redundant form. A comparator circuit is coupled with the arithmetic circuit to receive the result in redundant form and to perform an equality comparison of the result to the expected value, and to indicate the truth of said equality comparison independent of carry signal propagation from the least significant digit to the most significant digit.

6813628, Nov 2, 2004

Dec 22, 2000

09/746771

Bharat Bhushan - Cupertino CA
Edward Grochowski - San Jose CA
Vinod Sharma - Sunnyvale CA
John Crawford - Saratoga CA

Intel Corporation - Santa Clara CA

G06F 704

708671, 708200

A method and apparatus is disclosed to compare numbers for equality. The numbers represented in a redundant form, including numbers received from a bypass circuit are subtracted. More specifically, a complemented form is generated and supplied to an arithmetic circuit for at least one number represented in the redundant form. Input to the arithmetic circuit is adjusted to augment a result generated through the arithmetic circuit to generate a valid outcome represented in the redundant form as a result of a subtraction operation. Results of the subtraction operation are compared to zero in redundant form using a non-propagative circuit and without requiring carry propagation, thereby producing an equality comparison of the number in redundant form.

6826588, Nov 30, 2004

Dec 17, 2001

10/032026

Bharat Bhushan - Cupertino CA
Edward Grochowski - San Jose CA
Vinod Sharma - Sunnyvale CA
John Crawford - Saratoga CA

Intel Corporation - Santa Clara CA

G06F 702

708671

The present invention provides an efficient method for bypassing outputs while in redundant form to an arithmetic circuit that is capable of adding or subtracting numbers in redundant from and comparing the magnitudes of numbers received in redundant form for equality and inequality relationships. For one embodiment of the invention, an arithmetic circuit subtracts numbers received in redundant form and compares the result to zero represented in redundant form without carry propagation. In parallel with the subtraction and comparison, the most significant bits of each number received in redundant form are generated and compared for equality, and a carry-out is generated for the subtraction. These results are combined by magnitude comparison logic to produce a magnitude comparison for the numbers received in redundant form.