Vivek Joshi, 61Sunnyvale, CA

6559680, May 6, 2003

Nov 24, 1999

09/448250

Bharat Bhushan - Cupertino CA
Vivek Joshi - Sunnyvale CA

Intel Corporation - Santa Clara CA

H03K 19096

326 95, 326 83

A domino circuit may be provided with additional keeper transistors that are selectively activated when one of the input transistors in a logic structure has a low or inactive signal applied to it during the evaluation stage. Thus, the potential of the output node of the domino circuit may be maintained, improving the soft error rate.

6564328, May 13, 2003

Dec 23, 1999

09/471795

Edward T. Grochowski - San Jose CA
Vinod Sharma - Sunnyvale CA
Gregory S. Matthews - Santa Clara CA
Vivek Joshi - Sunnyvale CA
Ralph M. Kling - Sunnyvale CA

Intel Corporation - Santa Clara CA

G06F 126

713320

The present invention provides a digital-based mechanism for adjusting the power consumption in an integrated digital circuit such as a processor. The processor includes one or more functional units and a digital throttle that monitors activity states of the processors functional units to estimate the processors power consumption. One embodiment of the digital throttle includes one or more gate units, a monitor circuit, and a throttle circuit. Each gate unit controls the delivery of power delivery to a functional unit of the processor and provides a signal that indicates the activity state of its associated functional unit. The monitor circuit determines an estimated power consumption level from the signals and compares the estimated power consumption with a threshold power level. The throttle circuit adjusts the instruction flow in the processor if the estimated power consumption level exceeds the threshold power level.

6564331, May 13, 2003

Sep 24, 1999

09/405825

Vivek Joshi - Sunnyvale CA

Intel Corporation - Santa Clara CA

G06F 132

713324, 713300, 713322, 365230

A mechanism is provided for reducing the power consumption of a register file by disabling unused register file read ports. A selected entry of the register file is hardwired to zero and the address of the selected entry is driven to the address decoder of the register file in response to a power-down condition. The power-down condition occurs when, for example, no valid address is driven to the read port, i. e. the read port is unused. For one embodiment of the invention, the selected entry is the zero entry of the register file, and the address lines are grounded when an address valid bit associated with the read port is not asserted.

6593776, Jul 15, 2003

Aug 3, 2001

09/922434

Sudarshan Kumar - Fremont CA
Gaurav Mehta - Folsom CA
Vivek Joshi - Sunnyvale CA

Intel Corporation - Santa Clara CA

H03K 1994

326105, 326106, 326107, 326108

A decoder includes multiple decode gates, each to provide one bit of a decoded output signal. At least two of the decode gates share a transistor. According to one aspect, each of the multiple decode gates is a skewed gate.

6892284, May 10, 2005

Sep 11, 2002

10/242580

Jing Ling - Fremont CA, US
Juan-Carlos Calderon - Fremont CA, US
Jean-Michel Caia - San Francisco CA, US
Vivek Joshi - Sunnyvale CA, US
Anguo T. Huang - Mountain View CA, US
Steve J. Clohset - San Francisco CA, US

Intel Corporation - Santa Clara CA

G06F012/02

711153, 711170, 711171, 711172, 711173, 710 52, 710 56, 710 57, 707205, 707206

A memory is divided into a number of partitions. The partitions are grouped into a first group of partitions and a second group of partitions. When required by a port, a partition is assigned to the port from a pool of un-assigned partitions. The pool of un-assigned partitions comprises of un-assigned partitions from the first group of partitions and un-assigned partitions from the second group of partitions. The un-assigned partitions from the first group of partitions are assigned to the port until a first threshold is reached. The un-assigned partitions from the second group of partitions are assigned to the port after the first threshold is reached. A second threshold is used to limit a total number of partitions assigned to the port.

6944728, Sep 13, 2005

Dec 23, 2002

10/329283

Juan-Carlos Calderon - Fremont CA, US
Jean-Michel Caia - San Francisco CA, US
Vivek Joshi - Sunnyvale CA, US
Jing Ling - Fremont CA, US
Anguo T. Huang - Mountain View CA, US

Intel Corporation - Santa Clara CA

G06F012/00

711157, 711105, 710 53

Interleaving memory access includes enabling data included in a receive flow of data to be stored in a first memory bank, enabling data included in a transmit flow of data to be stored in a second memory bank, and alternating access of data in the first memory bank with access of data in the second memory bank.

7061867, Jun 13, 2006

Apr 2, 2002

10/115229

Anguo T. Huang - Mountain View CA, US
Jing Ling - Fremont CA, US
Jean-Michel Caia - San Fransico CA, US
Juan-Carlos Calderon - Fremont CA, US
Vivek Joshi - Sunnyvale CA, US

Intel Corporation - Santa Clara CA

H04J 1/16
H04L 1/00
H04L 12/26
G01R 31/08

370235, 370230, 370231, 370412, 3703951

The rate-based scheduling for a network application is used to control the bandwidth available to a flow while scheduling the transmission of the flow. The rate-based scheduling uses rate credits to represent the amount of data a flow is permitted to transmit and only permits a flow to transmit if the flow has rate credit available. A flow is permitted to transmit only if the peak packet rate for the scheduler has not been exceeded.

7065628, Jun 20, 2006

May 29, 2002

10/158409

Juan-Carlos Calderon - Fremont CA, US
Jing Ling - Fremont CA, US
Jean-Michel Caia - San Francisco CA, US
Vivek Joshi - Sunnyvale CA, US
Anguo T. Huang - Mountain View CA, US

Intel Corporation - Santa Clara CA

G06F 12/00

711173, 711129, 711135, 711156, 711171, 709215, 710 56, 710 57

Memory access efficiency for packet applications may be improved by transferring full partitions of data. The number of full partitions written to external memory may be increased by temporarily storing packets using on-chip memory that is on a chip with the processor. Before writing packets to external memory, packets of length smaller than the external memory partition size may be temporarily stored in the on-chip memory until an amount corresponding to a full or nearly full partition has been collected, at which point the data can be efficiently written to an external memory partition.