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Walter Thomas Esling, 645908 Terravista Dr, Austin, TX 78735

Walter Esling Phones & Addresses

5908 Terravista Dr, Austin, TX 78735    530-6726173   

El Dorado Hills, CA   

Colorado Spgs, CO   

Cameron Park, CA   

Monument, CO   

Orangevale, CA   

Fair Oaks, CA   

El Dorado, CA   

14833 Irondale Dr, Austin, TX 78717   

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Walter Thomas Esling

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Work

Company: Cirrus logic Jan 2017 Position: Principle member of technical staff verification

Education

Degree: Bachelors, Bachelor of Science School / High School: Oklahoma State University 1981 to 1985 Specialities: Electrical Engineering

Skills

Verilog • Debugging • Asic • Embedded Systems • Hardware • Semiconductors • Rtl Design • Hardware Architecture • Application Specific Integrated Circuits • Perl • Pcie • Soc

Languages

English

Industries

Computer Hardware

Mentions for Walter Thomas Esling

Walter Esling resumes & CV records

Resumes

Walter Esling Photo 2

Principle Member Of Technical Staff Verification

Location:
Austin, TX
Industry:
Computer Hardware
Work:
Cirrus Logic
Principle Member of Technical Staff Verification
Oracle Labs Aug 2011 - Dec 2016
Principle Member Technical Staff
Emulex 2003 - 2011
Principle Member Technical Staff
Wirecache 2001 - 2003
Principle Member Technical Staff
Endpoint Clinical 2000 - 2001
Principle Member of Technical Staff
Intel Corporation 1999 - 2000
Principle Member of Technical Staff
Sharewave Inc. 1998 - 1999
Senior Member of Technical Staff
Level One Communications 1995 - 1998
Senior Member of Technical Staff
Ford Microelectronics 1994 - 1995
Senior Member of Technical Staff
Ibm 1991 - 1994
Senior Member of Technical Staff
Hewlett-Packard 1985 - 1990
Senior Member of Technical Staff
Education:
Oklahoma State University 1981 - 1985
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Verilog, Debugging, Asic, Embedded Systems, Hardware, Semiconductors, Rtl Design, Hardware Architecture, Application Specific Integrated Circuits, Perl, Pcie, Soc
Languages:
English

Publications & IP owners

Us Patents

Method And Apparatus For Identifying Dependencies Within A Register

US Patent:
5768556, Jun 16, 1998
Filed:
Dec 22, 1995
Appl. No.:
8/577994
Inventors:
Miles Gaylord Canada - Colchester VT
Walter Esling - Colorado Springs CO
Jay Gerald Heaslip - Williston VT
Stephen William Mahin - Underhill VT
Pamela A. Wilcox - Burlington VT
James Hesson - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 900
G06F 928
US Classification:
395392
Abstract:
An apparatus for use with a computer system for identifying dependencies within a register, which dependencies are established by a succession of instructions for the computer system. The register includes a plurality of cells which may be in a hierarchical arrangement of register storage sets. In its preferred embodiment, the apparatus comprises a storage means for storing a bit map, which bit map is configured to provide bit map identifications identifying designated register storage sets. The bit map represents the hierarchical arrangement. The apparatus further comprises a logic means for logically treating information, which logic means is coupled with the storage means and with the computer system. The logic means receives a first bit map identification from a first instruction (the first bit map identification identifies a first register storage set), and receives a second bit map identification from a second instruction (the second bit map identification identifies a second register storage set. The second instruction is subsequent in the succession to the first instruction.

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