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Walter A Soto, 37Lakewood, CA

Known as:
Walter Arabid Soto Walter A Suto
Related to:
Hugo Alberto Soto 57 Elvira Reyes 59 Mauricio R Abrego 73 Lorenzo C Torres 57

Walter Soto Phones & Addresses

Lakewood, CA   

Long Beach, CA   

Norwalk, CA   

Phoenix, AZ   

Paramount, CA   

Bloomington, CA   

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Walter Soto resumes & CV records

Resumes

Walter Soto Photo 43

Walter Soto

Location:
United States
Walter Soto Photo 44

Ford Tamer

Position:
Ford Tamer at Ford Tamer
Location:
Orange County, California Area
Industry:
Telecommunications
Work:
Ford Tamer since Aug 2005
Ford Tamer

Publications & IP owners

Us Patents

Multi-Session Asymmetric Digital Subscriber Line Buffering And Scheduling Apparatus And Method

US Patent:
6707822, Mar 16, 2004
Filed:
Jan 7, 2000
Appl. No.:
09/479611
Inventors:
Jalil Fadavi-Ardekani - Newport CA
Walter G. Soto - Irvine CA
Weizhuang Xin - Aliso Viejo CA
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H04B 138
US Classification:
3703955, 370466, 370480, 375222
Abstract:
A transceiver for an asymmetric communication system is provided that implements a buffering and scheduling scheme that utilizes a virtual clock signal to synchronize processing of asynchronous frame data for multiple ADSL sessions. In every virtual clock cycle, the transceiver first sequentially performs transmit-processes for each active ADSL line and then sequentially performs receive-processes for each active ADSL line. An Asynchronous Transfer Mode (ATM) Acceleratol provides the network interface to multiple ATM channels and communicates frame data to a Frame Buffer (FB). The FB may be used in a ping-pang fashion for the communication of data between the ATM accelerator and a Framer/Coder/Interleaver (FCI), which performs its namesake, among other, functions. The FCI also interfaces a Digital Signal Processing (DSP) core through an Interleave/De-Interleave Memory (IDIM). The DSP core generates the virtual clock signal, which schedules operation of the ATM accelerator and the FCI.

Parameter Memory For Hardware Accelerator

US Patent:
6842844, Jan 11, 2005
Filed:
Feb 24, 2000
Appl. No.:
09/512511
Inventors:
Jalil Fadavi-Ardekani - Newport CA, US
Walter G. Soto - Irvine CA, US
Wayne Xin - Aliso Viejo CA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
G06F 1340
G06F 1517
G06F 15177
US Classification:
712 36, 712 35, 725 87, 725111, 711147, 711170
Abstract:
The present invention provides a hardware accelerator of a DSP with a parameter RAM memory for storing the parameters required for the various operating conditions of the accelerator. The hardware accelerator can easily and without modification accommodate design changes such as the need to support additional ADSL lines.

Optical Time Domain Reflectometry System And Method

US Patent:
2004007, Apr 15, 2004
Filed:
Oct 9, 2002
Appl. No.:
10/267760
Inventors:
John Iannelli - San Marino CA, US
Walter Soto - Irvine CA, US
International Classification:
G01N021/00
US Classification:
356/073100
Abstract:
A system for testing a fiber comprises a light source, such as a laser, that transmits light pulses into the fiber while the fiber is not carrying payload data, and a monitor photo diode that measures reflections from the light pulses. A driver system for the laser, comprises a driver circuit that operates a laser for transmitting data, a pulse generator for causing the laser to generate a series of pulses, and a switch for selecting either the driver circuit or the pulse generator to control the laser.

Possible Relatives

David Soto  Dalia C Soto  Daniel Soto  Delia M Soto  Denise Soto  Danielle A Soto  Dennise Soto  Walter J Last  Walter C Johnson  Walter J Stancil 

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