Wayne Lowell Burger, 92379 W Hester Rd, Cottontown, TN 37048

6744117, Jun 1, 2004

Feb 28, 2002

10/086061

Christopher P. Dragon - Tempe AZ
Wayne R. Burger - Phoenix AZ
Daniel J. Lamey - Phoenix AZ

Motorola, Inc. - Schaumburg IL

H01L 23552

257659, 257340, 438731

A semiconductor device ( ) having a gate ( ), a source ( ), and a drain ( ) with a gate bus ( ) and first ground shield ( ) patterned from a first metal layer and a second ground shield ( ) patterned from a second metal layer. The first ground shield ( ) and the second ground shield ( ) lower the capacitance of device ( ) making it suitable for high frequency applications and housing in a plastic package.

7525152, Apr 28, 2009

Feb 23, 2007

11/678330

Christopher P. Dragon - Tempe AZ, US
Wayne R. Burger - Phoenix AZ, US
Robert A. Pryor - Mesa AZ, US

Freescale Semiconductor, Inc. - Austin TX

H01L 29/76

257341, 257401, 257E2912

An RF power transistor with a metal design () comprises a drain pad () and a plurality of metal drain fingers () extending from the drain pad, wherein at least one metal drain finger comprises one or more sections of metal (-----), each section of metal including of one or more branch (-------) of metal having a metal width maintained within a bamboo regime.

7998852, Aug 16, 2011

Dec 4, 2008

12/328319

Jeffrey K. Jones - Chandler AZ, US
Margaret A. Szymanowski - Chandler AZ, US
Michele L. Miera - Gilbert AZ, US
Xiaowei Ren - Phoenix AZ, US
Wayne R. Burger - Phoenix AZ, US
Mark A. Bennett - Glasgow, GB
Colin Kerr - South Lanarkshire, GB

Freescale Semiconductor, Inc. - Austin TX

H01L 21/44

438612, 257786, 257E2159, 257E23023

Electronic elements (″) having an active device region () and bonding pad (BP) region () on a common substrate () desirably include a dielectric region underlying the BP () to reduce the parasitic impedance of the BP () and its interconnection () as the electronic elements (″) are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e. g. , oxide only) dielectric regions (′) can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region (″) having electrically isolated inclusions (′) of a thermal expansion coefficient (TEC) less than that of the dielectric material (″) in which they are embedded and/or closer to the substrate () TEC. For silicon substrates (), poly or amorphous silicon is suitable for the inclusions (″) and silicon oxide for the dielectric material (″). The inclusions (″) preferably have a blade-like shape separated by and enclosed within the dielectric material (″).

8071461, Dec 6, 2011

Dec 4, 2008

12/328325

Xiaowei Ren - Phoenix AZ, US
Wayne R. Burger - Phoenix AZ, US
Colin Kerr - South Lanarkshire, GB
Mark A. Bennett - Glasgow, GB

Freescale Semiconductor, Inc. - Austin TX

H01L 21/76

438425, 257368, 257379, 438430

Electronic elements (″) having an active device region () and integrated passive device (IPD) region () on a common substrate () preferably include a composite dielectric region (″) in the IPD region underlying the IPD () to reduce electromagnetic (E-M) () coupling to the substrate (). Mechanical stress created by plain dielectric regions (′) and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions (″) in the composite dielectric region (″) of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material (″) in the composite dielectric region (″). For silicon substrates (), non-single crystal silicon is suitable for the inclusions (″) and silicon oxide for the dielectric material (″). The inclusions (″) preferably have a blade-like shape separated by and enclosed within the dielectric material (″).

8134241, Mar 13, 2012

Jul 8, 2011

13/179295

Jeffrey K. Jones - Chandler AZ, US
Margaret A. Szymanowski - Chandler AZ, US
Michele L. Miera - Gilbert AZ, US
Xiaowei Ren - Phoenix AZ, US
Wayne R. Burger - Phoenix AZ, US
Mark A. Bennett - Glasgow, GB
Colin Kerr - South Lanarkshire, GB

Freescale Semiconductor, Inc. - Austin TX

H01L 23/48

257786, 257E2159, 257E23023

Electronic elements having an active device region and bonding pad (BP) region on a common substrate desirably include a dielectric region underlying the BP to reduce the parasitic impedance of the BP and its interconnection as the electronic elements are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e. g. , oxide only) dielectric regions can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region having electrically isolated inclusions of a thermal expansion coefficient (TEC) less than that of the dielectric material in which they are embedded and/or closer to the substrate TEC. For silicon substrates, poly or amorphous silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.

8283748, Oct 9, 2012

Oct 20, 2011

13/277847

Xiaowei Ren - Phoenix AZ, US
Wayne R. Burger - Phoenix AZ, US
Colin Kerr - South Lanarkshire, GB
Mark A. Bennett - Glasgow, GB

Freescale Semiconductors, Inc. - Austin TX

H01L 21/70

257506, 257E2902

Electronic elements having an active device region and integrated passive device (IPD) region on a common substrate preferably include a composite dielectric region in the IPD region underlying the IPD to reduce electro-magnetic (E-M) coupling to the substrate. Mechanical stress created by plain dielectric regions and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions in the composite dielectric region of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material in the composite dielectric region. For silicon substrates, non-single crystal silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.

2012003, Feb 16, 2012

Aug 12, 2010

12/855479

Paul W. Sanders - Scottsdale AZ, US
Wayne R. Burger - Phoenix AZ, US
Thuy B. Dao - Austin TX, US
Joel E. Keys - Austin TX, US
Michael F. Petras - Phoenix AZ, US
Robert A. Pryor - Mesa AZ, US
Xiaowei Ren - Phoenix AZ, US

FREESCALE SEMICONDUCTOR, INC. - Austin TX

H01L 27/06
H01L 21/82

257296, 257531, 438393, 257E27016, 257E21602

Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates () and lower resistance inductors (′) for the IC (). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors () and interconnections (--″) overlying the substrate (). The active transistor(s) (′) are formed in the substrate () proximate the front face (). Planar capacitors (′) are also formed over the front face () of the substrate (). Various terminals (------′, etc.) of the transistor(s) (′), capacitor(s) (′) and inductor(s) (′) are coupled to a ground plane () on the rear face () of the substrate () using through-substrate-vias (′) to minimize parasitic resistance. Parasitic resistance associated with the planar inductors (′) and heavy current carrying conductors (-′) is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC () previously unobtainable.

5578860, Nov 26, 1996

May 1, 1995

8/431948

Julio C. Costa - Phoenix AZ
Wayne R. Burger - Phoenix AZ
Natalino Camilleri - Tempe AZ
Christopher P. Dragon - Tempe AZ
Daniel J. Lamey - Phoenix AZ
David K. Lovelace - Chandler AZ
David Q. Ngo - Phoenix AZ

Motorola, Inc. - Schaumburg IL

H01L 2362
H01L 2976
H01L 2900

257528

A high frequency power FET device (22) is integrated with passive components (23,24,26,28,31), an electro-static discharge (ESD) device (27,127,227), and/or a logic structure (29) on a semiconductor body (13) to form a monolithic high frequency integrated circuit structure (10). The high frequency power FET device (22) includes a grounded source configuration. The logic structure (29) utilizes the high frequency power FET structure in a grounded source configuration as one device in a CMOS implementation.