Wayne Eric Burk, 511392 Cabrillo Ave, San Jose, CA 95132

6459428, Oct 1, 2002

Oct 3, 2001

09/970077

Wayne Eric Burk - San Jose CA
Yan Y. Tang - Mountain View CA
Michael G. Lavelle - Saratoga CA
Philip C. Leung - Fremont CA
Michael F. Deering - Los Altos CA
Ranjit S. Oberoi - Saratoga CA

Sun Microsystems, Inc. - Palo Alto CA

G06T 1500

345419

A graphics system configured to perform programmable filtering of samples to generate pixel values. The graphics system comprises a frame buffer, an accelerator unit and a video output processor. The accelerator unit receives graphics primitives, renders samples for the graphics primitives, and stores the rendered samples into a sample area of the frame buffer. The accelerator unit subsequently reads the samples from the sample area of the frame buffer, and filters the samples with a programmable filter having a programmable support region. The resulting pixel values are stored in a pixel area of the frame buffer. The video output processor reads the pixel values from the pixel area and converts the pixel values into a video signal which is provided to a video output port.

6731292, May 4, 2004

Mar 6, 2002

10/092016

Wayne Eric Burk - San Jose CA
Ewa M. Kubalska - San Jose CA
Brian D. Emberling - San Mateo CA

Sun Microsystems, Inc. - Santa Clara CA

G06F 1576

345519, 345520, 345531

An integrated circuit may include several components, one or more interfaces, an interconnect (e. g. , a bus), and a controller. The components may each be configured to assert a read request to read data stored externally to the integrated circuit. The interfaces may be configured to output the read request asserted by one of the components and to receive data in response to outputting the request. The interconnect may be coupled to perform one or more data transactions to transmit the data from one of the interfaces to one or more of the components. In response to the read request asserted by one of the components, the controller may inhibit performance of a read transaction initiated by the read request dependent upon a comparison of a total number of outstanding data transactions to a maximum allowable number of outstanding data transactions.

6842851, Jan 11, 2005

Feb 28, 2002

10/085642

Wayne Eric Burk - San Jose CA, US
Ewa M. Kubalska - San Jose CA, US
Brian D. Emberling - San Mateo CA, US

Sun Microsytems, Inc. - Santa Clara CA

G06F 1500

712225, 712218, 711167

A system and method for reading register contents from a computational pipeline having a plurality of computational units. The system includes a readback bus and a read control unit. The readback bus has a plurality of logic units coupled in a series. Each logic unit couples to a corresponding one of the computational units. The read control unit couples to each of the computational units through a corresponding load line, and is configured to assert a load signal on one of the load lines in response to a register read request. Each of the computational units is configured to transmit a data value from a selected register onto the readback bus in response to detecting an assertion of the load signal on its corresponding load line.

6873330, Mar 29, 2005

Mar 4, 2002

10/090490

Wayne Eric Burk - San Jose CA, US
David Gibbs - Oxnard CA, US
David Kehlet - Los Altos CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F015/16

345503, 714732, 714733

In one embodiment, a computer system includes a first component configured to output data on a bus in response to a request for data from a second component. The data output by the first component may include both the requested data and unrequested data, and the unrequested data may have an unpredictable value. A controller coupled to the bus may be configured to replace the unrequested data with data that has a predictable value. A signature analysis register included in the second component is configured to capture the requested data and the predictable data output by the controller. Thus, the signature captured in the second component may be predictable, despite the unpredictable data output by the first component.

6914609, Jul 5, 2005

Feb 28, 2002

10/085636

Yan Yan Tang - Mountain View CA, US
Wayne Eric Burk - San Jose CA, US
Philip C. Leung - Fremont CA, US

Sun Microsystems, Inc. - Santa Clara CA

G09G005/36

345557, 345530, 345537, 345552

A system and method for generating pixels for a display device. The system may include a sample buffer for storing a plurality samples in a memory, a sample cache for caching recently accessed samples, and a sample filter unit for filtering one or more samples to generate a pixel. The generated pixels may then be stored in a frame buffer or provided to a display device. The method operates to take advantage of the common samples shared by neighboring pixels in both the x and y directions for reduced sample buffer accesses and improved performance. The method involves reading samples from the memory that correspond to pixels in a plurality of neighboring scan lines, and possibly also to multiple pixels in each of these scan lines. The samples may be stored in a cache memory and then accessed from the cache memory for filtering. The method maximizes use of the common samples shared by neighboring pixels in both the x and y directions.