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Po C Chang7 Holly Ln UNIT 2, Tonawanda, NY 14150

Po Chang Phones & Addresses

Tonawanda, NY   

285 Perrymont Ave, San Jose, CA 95125    408-2958366   

San Francisco, CA   

Glendale, AZ   

Bakersfield, CA   

Mentions for Po C Chang

Po Chang resumes & CV records

Resumes

Po Chang Photo 33

Sales Director - America West Coast

Location:
Milpitas, CA
Industry:
Electrical/Electronic Manufacturing
Work:
Kemet Electronics Corporation
Sales Director - America West Coast
Kemet Electronics Corporation Apr 2015 - Jul 2017
Global Account Director
Kemet Electronics Corporation Jul 2012 - Jul 2015
Sales Manager
Tdk Jul 2005 - Jul 2012
Sales Manager
Education:
San Francisco State University 2002 - 2005
Bachelors, Marketing, Management
Skills:
Sales Management, Product Marketing, Manufacturing, International Sales, Electronics, Continuous Improvement, Management, Product Management, Key Account Management, Lean Manufacturing, Cross Functional Team Leadership, Business Development, New Business Development
Languages:
English
Po Chang Photo 34

Po Chang

Publications & IP owners

Us Patents

Efficient Encoding For Detecting Load Dependency On Store With Misalignment

US Patent:
2010016, Jul 1, 2010
Filed:
Mar 10, 2010
Appl. No.:
12/721164
Inventors:
Tse-yu Yeh - Cupertino CA, US
Daniel C. Murray - Morgan Hill CA, US
Po Yung Chang - Saratoga CA, US
Anup S. Mehta - Fremont CA, US
International Classification:
G06F 9/305
G06F 12/08
G06F 12/00
G06F 9/00
US Classification:
712224, 712300, 711144, 711E12037, 712E09018, 712E09001
Abstract:
In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation. The first even mask identifies bytes within the first even byte range that are written by the store memory operation, and wherein the first odd mask identifies bytes within the first odd byte range that are written by the store memory operation.

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