Wen F Fang, 612347 Winged Foot Rd, Half Moon Bay, CA 94019

2012018, Jul 26, 2012

Jan 25, 2011

13/012943

Wen Fang - Fremont CA, US

G06F 3/045

345174

A processing system configured for capacitive sensing comprises transmitter circuitry, a first internal diagnostic mechanism, and a determination module. The transmitter circuitry is configured to transmit during a first time period with a first transmitter path of a plurality of transmitter paths in an input device. Each transmitter path of the plurality of transmitter paths is configured for capacitive sensing. The first internal diagnostic mechanism comprises a selectable leakage path. The selectable leakage path is configured to be coupled with the transmitter circuitry. The determination module is configured to determine if a discontinuity exists within the first transmitter path based on a discharge rate for the first transmitter path. The discharge rate is acquired during a second time period via the selectable leakage path of the first internal diagnostic mechanism, wherein the second time period occurs after the first time period.

6219195, Apr 17, 2001

Jan 29, 1998

9/015733

Gani Jusuf - San Carlos CA
Wen Fang - Fremont CA

Marvell Technology Group Ltd.

G11B 502
G11B 509
G11B 1512

360 67

Low-noise magneto-resistive (MR) pre-amplifier circuit amplifies signal from MR head. MR head is biased at optimal point by current source to generate signal. Current source is powered by regulator to reduce noise contribution from Vcc due to finite output impedance of current source. Self-biased CMOS low-noise amplifier (LNA) minimizes input-referred noised without using negative power supply. Small MOS transistor with feedback tracking loop replaces self-bias resistor which determines lower corner cutoff frequency. This facilitates use of large-value resistor, thereby enabling on-chip integration of DC blocking input capacitor. Gm--Gm amplifier configuration increases gain bandwidth product and minimizes parasitic effects of MOS transistors.

5548250, Aug 20, 1996

Jan 5, 1995

8/368863

Wen Fang - Fremont CA

Cirrus Logic, Inc. - Fremont CA

H03L 707
H03L 708
H03L 710
H03L 716

331 14

According to the present invention, a PLL circuit is designed to include an active mode, a sleep mode and an idle mode. In the idle mode, the PLL draws substantially less power than that in the active mode. In order to return to the designed operating frequency immediately, the PLL periodically refreshes itself in this mode of operation. The power consumption of the PLL is dependent upon the ratio of on-time to off-time which is a fraction of the power consumed in the active mode. Preferably, the PLL is designed to receive an external clock signal as a reference clock from which it develops the internal system clock. The PLL also receives a lower frequency refresh signal for activating a refresh operation during the idle mode. The PLL can power itself down after completing a single phase compare operation. The refresh signal which can be derived from a real time clock must be synchronized to the external reference clock.

6242961, Jun 5, 2001

Oct 8, 1999

9/415680

James Liu - San Jose CA
Wen Fang - San Jose CA
Wen-Chung Wu - Cupertino CA

Altima Communication, Inc. - Irvine CA

H03L 500
H03K 501

327307

Circuits for the restoration of a drooped signal are disclosed. In the asynchronous mode circuit, the drooped signal can be restored by detecting the peak of the positive amplitude and the peak of the negative amplitude and take the difference between the two peaks. This difference signal is fed back the equalizer. In the synchronous mode circuit, the drooped signal is sliced and passed to a regeneration circuit. The regeneration circuit uses reference voltage signals and phase information from the slicer to generate a regenerated signal. The regenerated signal is compared with the equalized signal to generate a difference signal, again fed back to the equalizer. The sliced signal is also fed to a clock recovery circuit which recovers the clock signal embedded in the received signal. The two circuits can be combined to provide an optimal circuit for the restoration of a drooped signal.

2017004, Feb 16, 2017

Oct 28, 2016

15/338277

- San Jose CA, US
John M. WEINERTH - San Jose CA, US
Wen FANG - San Jose CA, US

Synaptics Incorporated - San Jose CA

G06F 3/044
G06F 3/041

A processing system comprises a sensing module, a first internal diagnostic mechanism, and a determination module. The sensing module is configured to couple with a first sensor electrode path of a plurality of sensor electrode paths, wherein the sensing module is configured to drive the first sensor electrode path with a first signal. The first internal diagnostic mechanism configured to couple with a second sensor electrode path and configured to acquire a test signal output while the sensing module drives the first sensor electrode path with the first signal. The first internal diagnostic mechanism comprises a selectable current source configured to couple with the second sensor electrode path, and wherein the selectable current source is enabled during acquisition of the test signal output. The determination module configured to determine whether the first and second sensor electrode paths are ohmically coupled together based on the test signal output.

2015030, Oct 22, 2015

Jun 30, 2015

14/788429

- San Jose CA, US
John M. WEINERTH - San Jose CA, US
Wen FANG - San Jose CA, US

SYNAPTICS INCORPORATED - San Jose CA

G06F 3/044
G06F 3/041

A processing system for a capacitive sensing input device comprises a sensing module, a first internal diagnostic mechanism, and a determination module. The sensing module is configured to couple with a first sensor electrode path of a plurality of sensor electrode paths, and is configured to drive the first sensor electrode path with a first signal. The first internal diagnostic mechanism is configured to couple with a second sensor electrode path and to acquire a test signal output while the sensing module drives the first sensor electrode path with the first signal. The first internal diagnostic mechanism comprises a selectable current source configured to couple with the second sensor electrode path, and the selectable current source is enabled during acquisition of the test signal output. The determination module is configured to determine whether the first and second sensor electrode paths are ohmically coupled together based on the test signal output.

2014015, Jun 12, 2014

Feb 13, 2014

14/180266

- San Jose CA, US
Wen FANG - Fremont CA, US

Synaptics Incorporated - San Jose CA

G01R 31/28

324548

A processing system configured for capacitive sensing comprises transmitter circuitry, a first internal diagnostic mechanism, and a determination module. The transmitter circuitry is coupled with a first transmitter path of a plurality of transmitter paths and configured to transmit a first transmitter signal with the first transmitter path, wherein each transmitter path of the plurality of transmitter paths is configured for capacitive sensing. The first internal diagnostic mechanism is coupled to a second transmitter path of the plurality of transmitter paths. The first internal diagnostic mechanism is configured to acquire a first resulting signal while the transmitter circuitry transmits the first transmitter signal with the first transmitter path, wherein the first internal diagnostic mechanism comprises a selectable leakage path coupled to the transmitter circuitry. The determination module is further configured to determine that the first transmitter path is ohmically coupled to the second transmitter path of the plurality of transmitter paths based upon the first resulting signal.