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Wen Kuan Fang, 611109 Littleoak Cir, San Jose, CA 95129

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1109 Littleoak Cir, San Jose, CA 95129   

188 Fumia Pl, San Jose, CA 95131   

Saint Cloud, FL   

Orlando, FL   

Kissimmee, FL   

Newark, CA   

Fremont, CA   

La Jolla, CA   

Alameda, CA   

Mentions for Wen Kuan Fang

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Resumes

Wen Fang Photo 30

Wen Fang

Wen Fang Photo 31

Tax Manager, Cpa

Location:
19199 De Havilland Dr, Saratoga, CA 95070
Industry:
Electrical/Electronic Manufacturing
Work:
Barracuda (Nyse: Cuda)
Tax Manager, Cpa
Sanmina Feb 2010 - 2013
Senior Tax Analyst
Bdo Usa, Llp Apr 2008 - Feb 2010
Tax Associate
Bdo Uk Llp 2008 - 2009
Tax Associate
Grant Thornton Llp Jan 2007 - Mar 2008
Tax Associate and Internship
Grant Thornton 2007 - 2007
Tax Associate
Xi'an Changfeng Science & Technology Industry Corp Jan 1996 - Jan 2002
Electrical Engineer
Education:
San Francisco State University 2005 - 2007
Masters
San Francisco State University
Masters, Bachelors, Business Administration, Electrical Engineering, Accounting
Skills:
Tax, Corporate Tax, Income Tax, Accounting, Tax Research, Financial Analysis, Financial Reporting, Tax Returns, Gaap, Fixed Assets
Certifications:
Cpa
Wen Fang Photo 32

Analog Mixed Signal Design Engineer

Location:
San Jose, CA
Industry:
Semiconductors
Work:
Avago Technologies
Analog Mixed Signal Design Engineer
Wen Fang Photo 33

Executive Manager

Industry:
Entertainment
Work:
Funfume
Executive Manager
Wen Fang Photo 34

Manager

Location:
San Jose, CA
Industry:
Real Estate
Work:

Manager
Wen Fang Photo 35

Wen Fang

Wen Fang Photo 36

Wen Fang

Wen Fang Photo 37

Wen Fang

Publications & IP owners

Us Patents

Input Device Transmitter Path Error Diagnosis

US Patent:
2012018, Jul 26, 2012
Filed:
Jan 25, 2011
Appl. No.:
13/012943
Inventors:
Wen Fang - Fremont CA, US
International Classification:
G06F 3/045
US Classification:
345174
Abstract:
A processing system configured for capacitive sensing comprises transmitter circuitry, a first internal diagnostic mechanism, and a determination module. The transmitter circuitry is configured to transmit during a first time period with a first transmitter path of a plurality of transmitter paths in an input device. Each transmitter path of the plurality of transmitter paths is configured for capacitive sensing. The first internal diagnostic mechanism comprises a selectable leakage path. The selectable leakage path is configured to be coupled with the transmitter circuitry. The determination module is configured to determine if a discontinuity exists within the first transmitter path based on a discharge rate for the first transmitter path. The discharge rate is acquired during a second time period via the selectable leakage path of the first internal diagnostic mechanism, wherein the second time period occurs after the first time period.

Low-Noise Magneto-Resistive Amplifier Using Cmos Technology

US Patent:
6219195, Apr 17, 2001
Filed:
Jan 29, 1998
Appl. No.:
9/015733
Inventors:
Gani Jusuf - San Carlos CA
Wen Fang - Fremont CA
Assignee:
Marvell Technology Group Ltd.
International Classification:
G11B 502
G11B 509
G11B 1512
US Classification:
360 67
Abstract:
Low-noise magneto-resistive (MR) pre-amplifier circuit amplifies signal from MR head. MR head is biased at optimal point by current source to generate signal. Current source is powered by regulator to reduce noise contribution from Vcc due to finite output impedance of current source. Self-biased CMOS low-noise amplifier (LNA) minimizes input-referred noised without using negative power supply. Small MOS transistor with feedback tracking loop replaces self-bias resistor which determines lower corner cutoff frequency. This facilitates use of large-value resistor, thereby enabling on-chip integration of DC blocking input capacitor. Gm--Gm amplifier configuration increases gain bandwidth product and minimizes parasitic effects of MOS transistors.

Low Power Phase Lock Loop Clocking Circuit For Battery Powered Systems

US Patent:
5548250, Aug 20, 1996
Filed:
Jan 5, 1995
Appl. No.:
8/368863
Inventors:
Wen Fang - Fremont CA
Assignee:
Cirrus Logic, Inc. - Fremont CA
International Classification:
H03L 707
H03L 708
H03L 710
H03L 716
US Classification:
331 14
Abstract:
According to the present invention, a PLL circuit is designed to include an active mode, a sleep mode and an idle mode. In the idle mode, the PLL draws substantially less power than that in the active mode. In order to return to the designed operating frequency immediately, the PLL periodically refreshes itself in this mode of operation. The power consumption of the PLL is dependent upon the ratio of on-time to off-time which is a fraction of the power consumed in the active mode. Preferably, the PLL is designed to receive an external clock signal as a reference clock from which it develops the internal system clock. The PLL also receives a lower frequency refresh signal for activating a refresh operation during the idle mode. The PLL can power itself down after completing a single phase compare operation. The refresh signal which can be derived from a real time clock must be synchronized to the external reference clock.

Methods And Circuits For Restoration Of A Drooped Dc Signal

US Patent:
6242961, Jun 5, 2001
Filed:
Oct 8, 1999
Appl. No.:
9/415680
Inventors:
James Liu - San Jose CA
Wen Fang - San Jose CA
Wen-Chung Wu - Cupertino CA
Assignee:
Altima Communication, Inc. - Irvine CA
International Classification:
H03L 500
H03K 501
US Classification:
327307
Abstract:
Circuits for the restoration of a drooped signal are disclosed. In the asynchronous mode circuit, the drooped signal can be restored by detecting the peak of the positive amplitude and the peak of the negative amplitude and take the difference between the two peaks. This difference signal is fed back the equalizer. In the synchronous mode circuit, the drooped signal is sliced and passed to a regeneration circuit. The regeneration circuit uses reference voltage signals and phase information from the slicer to generate a regenerated signal. The regenerated signal is compared with the equalized signal to generate a difference signal, again fed back to the equalizer. The sliced signal is also fed to a clock recovery circuit which recovers the clock signal embedded in the received signal. The two circuits can be combined to provide an optimal circuit for the restoration of a drooped signal.

Sensor Electrode Path Error Diagnosis

US Patent:
2017004, Feb 16, 2017
Filed:
Oct 28, 2016
Appl. No.:
15/338277
Inventors:
- San Jose CA, US
John M. WEINERTH - San Jose CA, US
Wen FANG - San Jose CA, US
Assignee:
Synaptics Incorporated - San Jose CA
International Classification:
G06F 3/044
G06F 3/041
Abstract:
A processing system comprises a sensing module, a first internal diagnostic mechanism, and a determination module. The sensing module is configured to couple with a first sensor electrode path of a plurality of sensor electrode paths, wherein the sensing module is configured to drive the first sensor electrode path with a first signal. The first internal diagnostic mechanism configured to couple with a second sensor electrode path and configured to acquire a test signal output while the sensing module drives the first sensor electrode path with the first signal. The first internal diagnostic mechanism comprises a selectable current source configured to couple with the second sensor electrode path, and wherein the selectable current source is enabled during acquisition of the test signal output. The determination module configured to determine whether the first and second sensor electrode paths are ohmically coupled together based on the test signal output.

Sensor Electrode Path Error Diagnosis

US Patent:
2015030, Oct 22, 2015
Filed:
Jun 30, 2015
Appl. No.:
14/788429
Inventors:
- San Jose CA, US
John M. WEINERTH - San Jose CA, US
Wen FANG - San Jose CA, US
Assignee:
SYNAPTICS INCORPORATED - San Jose CA
International Classification:
G06F 3/044
G06F 3/041
Abstract:
A processing system for a capacitive sensing input device comprises a sensing module, a first internal diagnostic mechanism, and a determination module. The sensing module is configured to couple with a first sensor electrode path of a plurality of sensor electrode paths, and is configured to drive the first sensor electrode path with a first signal. The first internal diagnostic mechanism is configured to couple with a second sensor electrode path and to acquire a test signal output while the sensing module drives the first sensor electrode path with the first signal. The first internal diagnostic mechanism comprises a selectable current source configured to couple with the second sensor electrode path, and the selectable current source is enabled during acquisition of the test signal output. The determination module is configured to determine whether the first and second sensor electrode paths are ohmically coupled together based on the test signal output.

Input Device Transmitter Path Error Diagnosis

US Patent:
2014015, Jun 12, 2014
Filed:
Feb 13, 2014
Appl. No.:
14/180266
Inventors:
- San Jose CA, US
Wen FANG - Fremont CA, US
Assignee:
Synaptics Incorporated - San Jose CA
International Classification:
G01R 31/28
US Classification:
324548
Abstract:
A processing system configured for capacitive sensing comprises transmitter circuitry, a first internal diagnostic mechanism, and a determination module. The transmitter circuitry is coupled with a first transmitter path of a plurality of transmitter paths and configured to transmit a first transmitter signal with the first transmitter path, wherein each transmitter path of the plurality of transmitter paths is configured for capacitive sensing. The first internal diagnostic mechanism is coupled to a second transmitter path of the plurality of transmitter paths. The first internal diagnostic mechanism is configured to acquire a first resulting signal while the transmitter circuitry transmits the first transmitter signal with the first transmitter path, wherein the first internal diagnostic mechanism comprises a selectable leakage path coupled to the transmitter circuitry. The determination module is further configured to determine that the first transmitter path is ohmically coupled to the second transmitter path of the plurality of transmitter paths based upon the first resulting signal.

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