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William J Bressette, 562188 Rudy Ct, Midland, MI 48642

William Bressette Phones & Addresses

2188 Rudy Ct, Midland, MI 48642    989-6879528   

2200 Rudy Ct, Midland, MI 48642    989-6877344   

Saginaw, MI   

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William Bressette resumes & CV records

Resumes

William Bressette Photo 17

William Bressette

Location:
Saginaw, Michigan Area
Industry:
Computer Software
William Bressette Photo 18

William Bressette

Publications & IP owners

Us Patents

Tachometer Apparatus And Method For Motor Velocity Measurement

US Patent:
6498409, Dec 24, 2002
Filed:
Sep 14, 2000
Appl. No.:
09/661657
Inventors:
Steven James Collier-Hallman - Frankenmuth MI
William J. Bressette - Midland MI
Assignee:
Delphi Technologies, Inc. - Troy MI
International Classification:
H02K 1100
US Classification:
310 68B, 310DIG 6, 324174
Abstract:
A method and apparatus for determining the velocity of a rotating device is described herein. The apparatus includes sets of sense magnets affixed to a rotating shaft of a rotating device and a circuit assembly. The circuit assembly includes a circuit interconnection having sense coils and sensors affixed thereto. The circuit assembly is adapted to place components thereon in close proximity to the sets of sense magnets on the rotating part.

Method And System For Motor Velocity Measurement

US Patent:
6791217, Sep 14, 2004
Filed:
Apr 4, 2002
Appl. No.:
10/116284
Inventors:
Steven James Collier-Hallman - Frankenmuth MI
William J Bressette - Midland MI
Assignee:
Delphi Technologies, Inc. - Troy MI
International Classification:
G01P 300
US Classification:
310 68B, 324163, 702145
Abstract:
A method and system for determining the velocity of a rotating device is described herein. The system includes an apparatus with a set of sense magnets affixed to a rotating shaft of the rotating device and a circuit assembly. The circuit assembly includes a circuit interconnection having a plurality of sense coils and sensors affixed thereto. The circuit assembly is adapted be in proximity to the set of sense magnets on the rotating part. A controller is coupled to the circuit assembly, where the controller executes an adaptive algorithm that determines the velocity of the rotating device. The algorithm is a method of combining a derived velocity with a velocity from the tachometer. The algorithm includes a plurality of functions including: receiving a position signal related to the rotational position of the shaft; determining a derived velocity from the position signal; generating a plurality of tachometer velocity signals; determining a compensated velocity in response to the plurality tachometer velocity signals; and blending the compensated velocity with derived velocity to generate a blended velocity output.

Massively Multiplexed Superscalar Harvard Architecture Computer

US Patent:
5655133, Aug 5, 1997
Filed:
Nov 13, 1995
Appl. No.:
8/558921
Inventors:
Wayne P. Dupree - Midland MI
Stephen G. Churchill - Midland MI
Jeffry R. Gallant - Midland MI
Larry A. Root - Midland MI
William J. Bressette - Saginaw MI
Robert A. Orr - Midland MI
Srikala Ramaswamy - Midland MI
Jeffrey A. Lucas - Midland MI
James A. Bleck - Midland MI
Assignee:
The Dow Chemical Company - Midland MI
International Classification:
G06F 930
US Classification:
39580023
Abstract:
A massively multiplexed central processing unit ("CPU") which has a plurality of independent computational circuits, a separate internal result bus for transmitting the resultant output from each of these computational circuits, and a plurality of general purpose registers coupled to each of the computational circuits. Each of the general purpose registers have multiplexed input ports which are connected to each of the result buses. Each of the general purpose registers also have an output port which is connected to a multiplexed input port of at least one of the computational circuits. Each of the computational circuits are dedicated to at least one unique mathematical function, and at least one of the computational circuits include at least one logical function. At least one of the computational circuits includes a plurality of concurrently operable mathematical and logical processing circuits, and an output multiplexer for selecting one of the resultant outputs for transmission on its result bus. The CPU also features a very long instruction word which uses a series of assigned bit locations to represent the selections codes for each of the CPU components.

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