William H Gascoyne, 66Aptos, CA

5552951, Sep 3, 1996

Jun 5, 1995

8/461133

Nicholas F. Pasch - Pacifica CA
William Gascoyne - San Jose CA

LSI Logic Corporation - Milpitas CA

H02H 322

361 56

A semiconductor circuit package includes features forming an electrostatic charge distribution network having nodes which are defined by the electrical contact leads of the package for the semiconductor circuit, and which are effectively connected with one another by spark-gaps. In one embodiment electrical leads of the package are provided with pointed protrusions lying in the plane of the electrical leads. Accordingly, an inadvertent electrostatic discharge is distributed throughout the semiconductor circuit at safe voltage levels determined by the characteristics of the spark gaps of the charge distribution network.

5068547, Nov 26, 1991

Sep 5, 1990

7/577945

William H. Gascoyne - San Jose CA

LSI Logic Corporation - Milpitas CA

H03K 513
H03K 5159

307443

In accordance with the present invention, a process monitor circuit and a method for monitoring a process are provided. The process monitor circuit provides first and second logic paths, the first logic path having a delay sensitive to whether the input logic transition is from logic high to logic low, or from logic low to logic high. The second logic path has substantially equal delays for either logic state transition. The two differences in delay between the first and second logic paths under the two logic state transitions are used to monitor the process steps for manufacturing the P and N transistors.

5886900, Mar 23, 1999

Sep 25, 1996

8/719508

William H. Gascoyne - San Jose CA
Jay S. Hidy - Saratoga CA

LSI Logic Gorporation

G06F 1750

364490

A method for providing a nonfunctional circuit design for evaluation in accordance with a static timing analysis is provided herein. The method initially generates a netlist, and then creates a standard delay format (SDF) file from the netlist. The standard delay format file contains occurrence names and delays associated with all elements of the design. The method subsequently selects elements of the design, alters the functionality of each selected element, and alters the standard delay format file entries corresponding to each selected element. The functional alteration of selected elements comprises altering an AND gate to be an OR gate, altering a NAND gate to be a NOR gate, altering an OR gate to be an AND gate, altering a NOR gate to be a NAND gate, altering an XOR to be an XNOR, and/or altering an XNOR to be an XOR in a predetermined manner. The method may accomplish random selection using a random number generator, or alternatively by visually selecting various design elements and altering the functionality of the gate as described. An alternative embodiment is disclosed wherein all elements having similar timing characteristics and different functionality are given identical functionality, such as all AND gates are changed to OR gates, so that all AND and OR gates have OR functionality.

5424896, Jun 13, 1995

Aug 12, 1993

8/105833

Nicholas F. Pasch - Pacifica CA
William Gascoyne - San Jose CA

LSI Logic Corporation - Milpitas CA

H02H 322

361 56

A semiconductor circuit package includes features forming an electrostatic charge distribution network having nodes which are defined by the electrical contact leads of the package for the semiconductor circuit, and which are effectively connected with one another by spark-gaps. In one embodiment electrical leads of the package are provided with pointed protrusions lying in the plane of the electrical leads. Accordingly, an inadvertent electrostatic discharge is distributed throughout the semiconductor circuit at safe voltage levels determined by the characteristics of the spark gaps of the charge distribution network.