Xiaoming Li, 581 Augusta Ct, Purchase, NY 10577

6643109, Nov 4, 2003

Sep 27, 2000

09/672165

Xiaoming Li - Irvine CA
Mark R. Tennyson - Irvine CA
Eugene R. Worley - Irvine CA

Conexant Systems, Inc. - Newport Beach CA

H02H 320

361 56, 361 915, 361111

An electrostatic discharge (ESD) protection circuit comprises a P-channel field effect transistor (PFET), a buffer and a damping network to provide improved protection for an integrated circuit against high-voltage ESD pulses. The ESD protection circuit is capable of being fabricated with a reduced surface area layout to be fully synthesisable with the integrated circuit which it is designed to protect.

6924196, Aug 2, 2005

Aug 6, 1999

09/370508

Umesh Sharma - Newport Beach CA, US
Kevin Q. Yin - Irvine CA, US
Hong J. Wu - Irvine CA, US
Suryanarayana Shivakumar Bhattacharya - Irvine CA, US
Xiaoming Li - Irvine CA, US

Newport Fab, LLC - Newport Beach CA

H01L021/336

438257, 438745, 438757

An anti-reflective coating for use in the fabrication of a semiconductor device includes a thin oxide layer and an overlying layer of silicon oxynitride. The anti-reflective layer is advantageously used in the fabrication of FLASH memory devices which include a layer of polycrystalline silicon and an underlying layer of silicon nitride. After being used to pattern the polycrystalline silicon and silicon nitride, the anti-reflective coating is removed in a solution of hot phosphoric acid with the removal taking place before the silicon oxynitride is exposed to any elevated temperatures.

7782582, Aug 24, 2010

Dec 19, 2007

11/959732

Xiaoming Li - Irvine CA, US

Mindspeed Technologies, Inc. - Newport Beach CA

H02H 3/20
H02H 9/00

361 56, 361111, 361 911

An electrostatic discharge (ESD) protection circuit includes an NPN transistor having a collector terminal connected to a voltage source and an emitter terminal connected to the ground via a diode. The NPN transistor includes a base terminal for receiving a base current to turn on the NPN transistor to allow an electrostatic discharge at the voltage source to flow through the NPN transistor to the ground. The ESD protection circuit further includes a PMOS transistor having a source terminal coupled to the voltage source and a drain terminal coupled to the base terminal of the NPN transistor. The PMOS transistor includes a gate terminal for receiving a first and a second gate voltage. The ESD protection circuit further includes an R-C circuit coupled between the source voltage and the ground. The R-C circuit is configured to supply the first gate voltage to the PMOS transistor when there is no electrostatic discharge to turn off the PMOS transistor and the second gate voltage responsive to the electrostatic discharge to turn on the PMOS transistor for a predetermined time period. The ESD protection circuit further includes a voltage divider circuit coupled between the voltage source and the ground and coupled to the R-C circuit.

8030719, Oct 4, 2011

May 8, 2009

12/387892

Xiaoming Li - Irvine CA, US
Surinderjit Dhaliwal - Laguna Niguel CA, US

Mindspeed Technologies, Inc. - Newport Beach CA

H01L 29/82

257425, 257428, 257E31131

There is provided a semiconductor package that includes a first semiconductor die mounted on a package substrate. The semiconductor package further includes a second semiconductor die mounted on the first semiconductor die and including a thermal sensing and reset protection circuit. The thermal sensing and reset protection circuit is configured to determine a temperature of the first semiconductor die and to provide a reset protection signal to the first semiconductor die when the temperature of the first semiconductor die is substantially equal to a preset temperature so as to protect the first semiconductor die from thermal runaway. The reset protection signal can cause the first semiconductor die to be in a sleep mode or a reset state.

2009027, Nov 5, 2009

Apr 27, 2009

12/387133

Xiaoming Li - Irvine CA, US

H01L 23/49
H01L 23/488
H01L 21/60

257692, 257784, 438121, 257E23023, 257E23024, 257E21509

Semiconductor dies embodying electronic circuits are enclosed and protected within a package. To electrically access the die, the package includes external electrical leads which in turn connect to internal bond wires. The bond wires electrically connect the package to the die. As die density and circuit complexity increase, bond wire are placed in greater proximity. As a result, signal coupling between adjacent bond wires also increases and this coupling reduces circuit performance and input/output rates. A dissipation bond wire is provided adjacent the signal or supply bond wire acting as an aggressor. The dissipation bond wire has a first end connecting to the package and the second end connecting to the die or the package to form a conductive loop which dissipates unwanted coupling from an aggressor bond wire before the coupling couples into victim bond wire. The dissipation bond wire may be grounded.

2011016, Jul 14, 2011

Jan 8, 2010

12/655879

Xiaoming Li - Irvine CA, US
Surinderjit S. Dhaliwal - Laguna Niguel CA, US

MINDSPEED TECHNOLOGIES, INC. - NEWPORT BEACH CA

G05F 3/02
H01L 23/52

327540, 257691, 257723, 257E23141

There is provided a semiconductor package configured for externally controlled power management. Instead of integrating voltage regulation on-chip as done conventionally, power regulation is moved externally to the PCB level, providing numerous package advantages including size, simplicity, power efficiency, integration flexibility, and thermal dissipation. In particular, the use of flip-chip package configurations provides ready access to power supply bumps, which also allows the use of a universal receiving PCB and power supply through simple reconfiguring of voltage traces. As a result, flexible power management can be implemented, and portions of semiconductor packages may be managed for performance or thermal considerations, which may be of particular use for applications such as multi-core processors.

2011017, Jul 14, 2011

Jan 8, 2010

12/655881

Xiaoming Li - Irvine CA, US
Surinderjit S. Dhaliwal - Laguna Niguel CA, US

MINDSPEED TECHNOLOGIES, INC. - Newport Beach CA

G06F 1/32
G06F 1/26
G06F 9/46

713324, 713300, 718102, 713320

There is provided a method of scheduler assisted power management for semiconductor devices. By accessing and analyzing workload data for tasks to be completed, a scheduler may provide finer grained control for determining and implementing an efficient power management policy. In this manner, tasks with completion deadlines can be allocated sufficient resources without wasteful power consumption resulting from ramping up of performance through overestimating of voltage or frequency increases. Additionally, power management may be planned for longer periods, rather than looking only at immediate data to be processed and constantly fluctuating voltage and frequency. In this manner, power management can run more smoothly and efficiently compared to conventional means of power management that ignore data from a scheduler when determining power management policy.

5781788, Jul 14, 1998

Sep 29, 1997

8/939997

Xiaoming Li - Yorktown Heights NY
Vivian Hsiun - Palo Alto CA

AVC Technology, Inc. - Cupertino CA

G06F 1300

39580001

A single-chip video compression/decompression (video codec) chip is connected to receive a video input from a NTSC-compatible or PAL-compatible camera and a transmit channel. Video information from the camera or other video input source is compressed by the video codec and transmitted out in compressed form on a transmit channel. Concurrently, compressed video information is input to the video codec from a receive channel, decompressed and output to the monitor or other video output device, e. g. , a television set. Only a separate single module of dynamic random access memory (DRAM) is needed to provide storage for incoming and outgoing video data, compressed bit streams and reconstructed pictures for both compression and decompression procedures. The compression of video information is by spatial decorrelation of the intraframe information, and temporal decorrelation of the interframe information. The communication channel bit rate is further reduced by quantization and variable length coding.