Xiaoqing Xu, 5446 Victoria Ct, Niskayuna, NY 12309

2022027, Aug 25, 2022

Dec 3, 2021

17/542024

Daniel CHANEMOUGAME - Albany NY, US
Lars LIEBMANN - Albany NY, US
Jeffrey SMITH - Albany NY, US
Paul GUTWIN - Albany NY, US
Xiaoqing XU - Austin TX, US

H01L 27/092
H01L 29/66
H01L 29/786
H01L 21/02
H01L 29/423
H01L 21/8238
H01L 29/06
H01L 23/528

Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first semiconductor device tier that includes first semiconductor devices. A first signal wiring structure can be formed over and electrically connected to the first semiconductor device tier. An insulator layer can be formed over the first signal wiring structure. A second semiconductor device tier can be formed over the insulator layer, the second semiconductor device tier including second semiconductor devices. A second signal wiring structure can be formed over and electrically connected to the second semiconductor device tier. An inter-tier via can be formed vertically through the insulator layer and electrically connecting the second signal wiring structure to the first signal wiring structure. The first semiconductor device tier, the second semiconductor device tier and the inter-tier via can be formed monolithically.

2022018, Jun 9, 2022

Dec 3, 2021

17/541561

Lars LIEBMANN - Mechanicsville NY, US
Jeffrey SMITH - Clifton Park NY, US
Daniel CHANEMOUGAME - Niskayuna NY, US
Paul GUTWIN - Williston VT, US
Brian CLINE - Austin TX, US
Xiaoqing XU - Austin TX, US
David PIETROMONACO - San Jose CA, US

H01L 23/538
H01L 23/498
H01L 25/065
H01L 23/48
H01L 25/00

Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a lower semiconductor device tier, and a lower signal wiring structure electrically connected to the lower semiconductor device tier. The multi-tier semiconductor structure can further include a primary power delivery network (PDN) structure disposed over the lower semiconductor device tier and the lower signal wiring structure and electrically connected to the lower semiconductor device tier. The multi-tier semiconductor structure can further include an upper semiconductor device tier disposed over and electrically connected the first PDN structure, and an upper signal wiring structure disposed over the primary PDN structure and electrically connected to the upper semiconductor device tier.

2022018, Jun 9, 2022

Dec 3, 2021

17/541581

Lars LIEBMANN - Mechanicsville NY, US
Jeffrey SMITH - Clifton Park NY, US
Daniel CHANEMOUGAME - Niskayuna NY, US
Paul GUTWIN - Williston VT, US
Brian CLINE - Austin TX, US
Xiaoqing XU - Austin TX, US
David PIETROMONACO - San Jose CA, US

H01L 25/065
H01L 25/00
H01L 25/18
H01L 23/528

Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first power delivery network (PDN) structure, and a first semiconductor device tier disposed over and electrically connected to the first PDN structure. The multi-tier semiconductor structure can further include a signal wiring tier disposed over and electrically connected to the first semiconductor device tier, a second semiconductor device tier disposed over and electrically connected to the signal wiring tier, and a second PDN structure disposed over and electrically connected to the second semiconductor device tier. The multi-tier semiconductor structure can further include a through-silicon via (TSV) structure electrically connected to the signal wiring tier, wherein the TSV structure penetrates the second PDN structure.

2022018, Jun 9, 2022

Dec 3, 2021

17/541609

Lars LIEBMANN - Mechanicsville NY, US
Jeffrey SMITH - Clifton Park NY, US
Daniel CHANEMOUGAME - Niskayuna NY, US
Paul GUTWIN - Williston VT, US
Brian CLINE - Austin TX, US
Xiaoqing XU - Austin TX, US
David PIETROMONACO - San Jose CA, US

H01L 27/06
H01L 27/092

A semiconductor device includes a first pair of transistors over a substrate. The first pair of transistors includes a first transistor having a first gate structure over the substrate and a second transistor having a second gate structure stacked over the first transistor. A second pair of transistors is stacked over the first pair of transistors, resulting in a vertical stack perpendicular to a working surface of the substrate. The second pair of transistors includes a third transistor having a third gate structure stacked over the second transistor and a fourth transistor having a fourth gate structure stacked over the third transistor. The third gate structure extends from a central region of the vertical stack to a first side of the vertical stack. The second gate structure and the fourth gate structure extend from the central region to a second side of the vertical stack opposite the first side.