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Xiaowei Zhu, 40Irvine, CA

Known as:
Xiao Wei Zhu
Related to:
Gordon Hu 28 Shirley J Hu 23

Xiaowei Zhu Phones & Addresses

Irvine, CA   

Marina del Rey, CA   

Culver City, CA   

Plano, TX   

Sammamish, WA   

Work

Company: Lkp Global Law, LLP Address: 1901 Avenue Of The Stars, Suite 480, Los Angeles, CA 90067

Education

School / High School: University of Southern California Law School

Ranks

Licence: New York - Currently registered Date: 2010
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Career records & work history

Lawyers & Attorneys

Xiaowei Zhu Photo 1

Xiaowei Zhu, Los Angeles CA - Lawyer

Address:
Lkp Global Law, LLP
1901 Avenue Of The Stars, Suite 480, Los Angeles, CA 90067
213-6105066 (Office)
Licenses:
New York - Currently registered 2010
Education:
University of Southern California Law School

Xiaowei Zhu resumes & CV records

Resumes

Xiaowei Zhu Photo 18

Xiaowei Zhu

Xiaowei Zhu Photo 19

Xiaowei Zhu

Publications & IP owners

Us Patents

Method Of Fabricating An Integrated Circuit To Improve Soft Error Performance

US Patent:
7523422, Apr 21, 2009
Filed:
Mar 7, 2007
Appl. No.:
11/683278
Inventors:
Xiaowei Zhu - Plano TX, US
Robert C. Baumann - Dallas TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 17/50
H03K 19/003
US Classification:
716 2, 716 4, 326 10
Abstract:
The present invention provides, in one aspect, a method of designing an integrated circuit. In this particular aspect, the method comprises reducing soft error risk in an integrated circuit by locating a structure, relative to a node of the integrated circuit to reduce a linear energy transfer associated with a sub-atomic particle, into the node, such that the linear energy transfer does not exceed a threshold value associated with the integrated circuit.

Mitigation Of Charge Sharing In Memory Devices

US Patent:
7855907, Dec 21, 2010
Filed:
Dec 18, 2008
Appl. No.:
12/338393
Inventors:
Xiaowei Zhu - Plano TX, US
Xiaowei Deng - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G11C 5/02
US Classification:
365 51, 365174, 365177
Abstract:
One embodiment relates to a memory element disposed on a substrate. The memory element includes first and second interlocked data storage elements adapted to cooperatively store the same datum. An output of the first data storage element is coupled to an input node of the second data storage element. An output of the second data storage element is coupled to an input of the first data storage element. An isolation element in the substrate is arranged laterally between storage nodes of the first and second data storage elements. The isolation element is arranged to limit charge sharing between the storage nodes of the first and second data storage elements. Other methods and systems are also disclosed.

Power-Saving Retention Mode

US Patent:
2006003, Feb 9, 2006
Filed:
Aug 3, 2004
Appl. No.:
10/910440
Inventors:
Xiaowei Zhu - Plano TX, US
Claude Cirba - Plano TX, US
International Classification:
G01R 31/30
G06F 11/00
US Classification:
714745000
Abstract:
Embodiments of the invention are disclosed wherein methods and systems are provided for implementing a power-saving retention mode in an integrated circuit having both logic elements and memory elements. The methods of the invention include steps for scanning at least some of the logic elements of the integrated circuit and writing the states of the scanned logic elements to memory elements. Upon entering a retention mode, the scanned logic elements of the integrated circuit are powered down to conserve power. Transitioning from retention mode to active mode, the logic elements of the integrated circuit are again powered up and the scanned logic states are restored to the logic elements from the memory elements. Also disclosed is the implementation of the invention in combination with known power-saving techniques.

Method Of Fabricating And Integrated Circuit To Improve Soft Error Performance

US Patent:
2006015, Jul 6, 2006
Filed:
Jan 6, 2005
Appl. No.:
11/030273
Inventors:
Xiaowei Zhu - Plano TX, US
Robert Baumann - Dallas TX, US
Assignee:
Texas Instruments, Incorporated - Dallas TX
International Classification:
G06F 17/50
US Classification:
716004000
Abstract:
The present invention provides, in one aspect, a method of designing an integrated circuit . In this particular aspect, the method comprises reducing soft error risk in an integrated circuit by locating a structure relative to a node of the integrated circuit to reduce a linear energy transfer associated with a sub-atomic particle into the node , such that the linear energy transfer does not exceed a threshold value associated with the integrated circuit

Possible Relatives

Dawei I Zhu  Dehua Zhu  Di Zhu  Dian C Zhu  Diana Zhu  Dong Zhu  Dongming Zhu  Xiaowei I Liu  Xiaowei Xu  Xiaowei Yin 

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