Xu Zhang, 36863 E Parkview Dr, Gilbert, AZ 85295

2023005, Feb 23, 2023

Aug 19, 2021

17/406405

- Austin TX, US
Xu Zhang - Chandler AZ, US
Xiaoquin Liu - Chandler AZ, US

H03K 19/0175
H04L 25/02

Various embodiments relate to a transmit driver circuit, including: a first node connected to a first differential output; a first transistor connected in series with a first resistor, wherein the series connected first transistor and first resistor are connected between a source voltage and the first node; a second transistor connected in series with a second resistor, wherein the series connected second transistor and second resistor are connected between the first node and a ground; a second node connected to a second differential output; a third transistor connected in series with a third resistor, wherein the series connected third transistor and third resistor are connected between the source voltage and the second node; a fourth transistor connected in series with a fourth resistor, wherein the series connected fourth transistor and fourth resistor are connected between the second node and the ground; a first differential input connected to the gate of the first transistor and the gate of the fourth transistor; and a second differential input connected to the gate of the second transistor and the gate of the third transistor, wherein the first transistor, second transistor, third transistor, and fourth transistor are NMOS transistors.

2021035, Nov 18, 2021

May 18, 2020

16/876970

- Eindhoven, NL
Xu Zhang - Chandler AZ, US
Tong Liu - College Station TX, US
Samuel Michael Palermo - College Station TX, US

H04L 25/03

A continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes a passive CTLE circuit and an active CTLE circuit. The active CTLE circuit includes a differential transistor pair and the output of the passive CTLE is configured to drive gates or bases of the differential transistor pair.

2020014, May 7, 2020

Nov 7, 2018

16/183724

- Eindhoven, NL
Xu ZHANG - Chandler AZ, US

H03K 19/003
H03K 17/284

An integrated circuit delay cell includes an input circuit to establish a current level in the circuit, a switch configured to control an on/off time of a delay circuit, a delay circuit including at least one current starved stage configured to mirror the current level, the delay circuit configured to control a speed of a rise and/or fall time of an output signal, and a glitch discharging circuit connected to the delay circuit configured to tolerate and discharge unwanted charge of the delay circuit.

2019002, Jan 17, 2019

Jul 17, 2017

15/652033

- Eindhoven, NL
Ahmad YAZDI - Chandler AZ, US
Stefan KWAAITAAL - Waaire, NL
Cor SPEELMAN - Wijchen, NL
Xu ZHANG - Chandler AZ, US

H02H 9/04
H02H 1/00
H01R 24/64

A clamp circuit disposed between a receptacle and a circuit to be protected when a connector connects to the receptacle, the clamp circuit including a voltage detector configured to determine a level of a surge voltage in comparison to a threshold voltage, the voltage detector including a plurality of field effect transistors (FETs) of a first conductivity type connected in series, a first FET of a second conductivity type and a first resistor in parallel with the plurality of FETs, a second FET of the first conductivity type in parallel with the first FET, and a discharge circuit to discharge the surge voltage when the surge voltage approaches the threshold voltage.

2015018, Jun 25, 2015

Apr 28, 2014

14/263814

- Eindhoven, NL
Xu Zhang - Chandler AZ, US

NXP B.V. - Eindhoven

H03K 17/0412
H03K 3/012

Switching circuits are implemented in a manner that facilitates fast switching, which can be effected while also maintaining relatively low power dissipation. As may be implemented in connection with one or more embodiments, an apparatus includes a transistor connected between an input port and an output port, and a gate that switches between on and off states. A charge storage circuit stores a charge, and a switching circuit operates by switching the transistor between the on and off states as follows. In a first charging mode, a voltage is coupled across the charge storage circuit and a charge is stored therein, while decoupling the transistor from the charge storage circuit. In a second discharge mode, the transistor is switched from the off state to the on state, while coupling the stored charge across the gate and one of the source and drain of the transistor.

2015018, Jun 25, 2015

Apr 18, 2014

14/256799

- Eindhoven, NL
Xu Zhang - Chandler AZ, US

NXP B.V. - Eindhoven

H03K 17/14

Various example embodiments are directed to methods and circuits for mitigation of on-resistance variation and signal attenuation in transistors due to body effects. In some embodiments, an apparatus includes a transistor configured to provide a data signal from a first one of the source or the drain to the other one of the source or the drain in response to a control signal provided to the gate. A body bias circuit is configured to bias the body of the transistor based on a voltage of the data signal to reduce variation in the on-resistance exhibited by the first transistor. As a result of the reduced variation in the on resistance, attenuation of the data signal is reduced.

2015016, Jun 18, 2015

Apr 10, 2014

14/250168

- Eindhoven, NL
James Spehar - Chandler AZ, US
Xu Zhang - Chandler AZ, US

NXP B.V. - Eindhoven

G06F 17/50
H01L 23/495

Various example embodiments are directed to methods and apparatuses for implementing a circuit design within an integrated circuit (IC) package. A respective capacitance is determined for each die contact of a circuit design. A respective target inductance range is selected for each of the plurality of die contacts based on the determined capacitance. A segmentation of the circuit design is determined as a function of the target inductance ranges. The segmentation defines an implementation of the circuit design on a plurality of IC dies. The IC dies are placed at respective locations on the substrate, based on the resulting inductances of connections (e.g., conductive traces) between the die contacts and terminals of the IC package.