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Yanli Zhang11210 Taylor Crst, San Antonio, TX 78249

Known as:
Yan Lizhang
Related to:
Jun Bai Jiajun Yajie Zhang 56

Yanli Zhang Phones & Addresses

San Antonio, TX   

San Francisco, CA   

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Yanli Zhang resumes & CV records

Resumes

Yanli Zhang Photo 19

Software Engineer

Location:
San Francisco, CA
Industry:
Computer Software
Work:
Shutterfly, Inc.
Software Engineer
Education:
Qilu High School 5
Skills:
Java, Software Project Management, Requirements Analysis, Javascript, Testing, Business Analysis, Quality Assurance, Pre Sales
Yanli Zhang Photo 20

Display System Engineer

Location:
1056 Wallace Dr, San Jose, CA 95120
Industry:
Semiconductors
Work:
Intel Corporation 2016 - Aug 2017
Display Technologist Apple 2016 - Aug 2017
Display System Engineer Intel Corporation 2016 - 2016
Senior Staff Display System Architect Intel Corporation Apr 2011 - Apr 2013
Display Exploration Engineer Intel Corporation Jul 2005 - Apr 2011
Display System Engineer Ibm Technology Product 1999 - 2000
Process Engineer Shenzhen Jinghua Displays Co., Ltd. 1998 - 1999
Process Engineer
Education:
Kent State University 2000 - 2005
Doctorates, Doctor of Philosophy, Physics Shanghai Jiao Tong University 1995 - 1998
Master of Science, Masters
Skills:
Optics, Thin Films, Semiconductors, Materials Science, Color Management, Display Technology, Digital Image Processing, 3D Displays, Display System, Display Measurement
Yanli Zhang Photo 21

Director, 3D Memory Technology

Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Western Digital
Director, 3D Memory Technology Sandisk Jan 2016 - Jul 2018
Senior Manager, 3D Nand Technology Sandisk Apr 2015 - Mar 2016
Manager, 3D Nand Technology Sandisk Mar 2012 - Jan 2015
Senior Staff Engineer, 3D Nand Technology Ibm May 2008 - Mar 2012
Engineer, Cmos Soi Technology
Education:
Lehigh University 2004 - 2008
Doctorates, Doctor of Philosophy, Electrical Engineering University of Science and Technology of China 2001 - 2004
Masters, Physics, Electronics
Skills:
Cmos, Semiconductors, Process Integration, Simulations, Characterization, Device Characterization, Ic, Tcad, Circuit Design, Semiconductor Device, Physics, Semiconductor Device Physics, Device Modeling, Embedded Systems, Device Design, Spice, Silicon, Algorithms
Languages:
English
Mandarin

Publications & IP owners

Us Patents

Method And Apparatus For Adaptive Black Frame Insertion

US Patent:
8358260, Jan 22, 2013
Filed:
Apr 6, 2009
Appl. No.:
12/384500
Inventors:
Akihiro Takagi - San Mateo CA, US
Cheng-Shih Chin - Campbell CA, US
Yanli Zhang - San Jose CA, US
Maximino Vasquez - Fremont CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G09G 3/36
US Classification:
345 98, 345 88, 345 89, 345 92, 345 94, 345102
Abstract:
A display device may include a flat panel display, and a controller coupled to the flat panel display. The controller may be configured to determine an operating mode for the flat panel display among a plurality of operating modes including at least a first operating mode and a second operating mode. In the first operating mode, the controller may set the flat panel display to utilize a first frame rate and a first inversion mode to save power. In the second operating mode, the controller may set the flat panel display to utilize a second frame rate, a second inversion mode, and a black frame insertion to improve image quality. The second frame rate may be faster than the first frame rate. The second inversion mode and black frame insertion may be mutually configured to maintain a DC balanced operation of the flat panel display.

Power Efficient High Frequency Display With Motion Blur Mitigation

US Patent:
8578192, Nov 5, 2013
Filed:
Jun 30, 2008
Appl. No.:
12/165249
Inventors:
Maximino Vasquez - Fremont CA, US
Akihiro Takagi - San Mateo CA, US
Yanli Zhang - San Jose CA, US
Achintya K. Bhowmik - Milpitas CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/32
G09G 5/00
US Classification:
713320, 345211, 345212
Abstract:
Some embodiments describe techniques that relate to power efficient, high frequency displays with motion blur mitigation. In one embodiment, the refresh rate of a display device may be dynamically modified, e. g. , to reduce power consumption and/or reduce motion blur. Other embodiments are also described.

Using Spatial Distribution Of Pixel Values When Determining Adjustments To Be Made To Image Luminance And Backlight

US Patent:
2008023, Oct 2, 2008
Filed:
Mar 29, 2007
Appl. No.:
11/693272
Inventors:
Maximino Vasquez - Fremont CA, US
Yanli S. Zhang - San Jose CA, US
Kristine Karnos - San Jose CA, US
International Classification:
G09G 3/36
US Classification:
345102
Abstract:
A method of adjusting the display of data oh a flat panel display may include ascertaining color value information and spatial distribution information for pixels in an image. A desired image adjustment and a desired backlight adjustment may be determined based on both the color value information and spatial distribution information. The method may also include adjusting color values of at least some pixels in the image based on the desired image adjustment and controlling a backlight intensity based on the desired backlight adjustment.

Method And Apparatus For Reducing Power Consumption For Displays

US Patent:
2009032, Dec 31, 2009
Filed:
Jun 30, 2008
Appl. No.:
12/164704
Inventors:
Maximino Vasquez - Fremont CA, US
Achintya Bhowmik - Milpitas CA, US
Yanli Zhang - San Jose CA, US
Akihiro Takagi - San Mateo CA, US
International Classification:
G09G 5/10
US Classification:
345690, 382168
Abstract:
A system, apparatus and method to reduce power consumption for displays is described. The method may include receiving image data comprising a plurality of color components, generating a histogram for each of the plurality of color components, and adjusting each of a plurality of light sources based on the histograms. The plurality of light sources may correspond to the plurality of color components. Other embodiments are described and claimed.

Method And Apparatus For Adaptive Black Frame Insertion

US Patent:
2013011, May 9, 2013
Filed:
Dec 28, 2012
Appl. No.:
13/729606
Inventors:
Akihiro Takagi - San Mateo CA, US
Cheng-Shih Chin - Campbell CA, US
Yanli Zhang - San Jose CA, US
Maximino Vasquez - Fremont CA, US
International Classification:
G09G 3/36
US Classification:
345 89
Abstract:
In some embodiments, a display device may include a flat panel display a controller coupled to the flat panel display. The controller may be configured to determine an operating mode for the flat panel display among a plurality of operating modes including at least a first operating mode and a second operating mode. In the first operating mode, the controller may set the flat panel display to utilize a first frame rate and a first inversion mode to save power. In the second operating mode, the controller may set the flat panel display to utilize a second frame rate, a second inversion mode, and black frame insertion to improve image quality. The second frame rate may be faster than the first frame rate. The second inversion mode and black frame insertion may be mutually configured to maintain a DC balanced operation of the flat panel display. Other embodiments are disclosed and claimed.

Method And Apparatus For Reducing Power Consumption For Displays

US Patent:
2013032, Dec 12, 2013
Filed:
Aug 12, 2013
Appl. No.:
13/965095
Inventors:
Maximino Vasquez - Fremont CA, US
Achintya Bhowmik - Milpitas CA, US
Yanli Zhang - San Jose CA, US
Akihiro Takagi - San Mateo CA, US
International Classification:
G09G 5/04
US Classification:
345690, 345 88
Abstract:
A system, apparatus and method to reduce power consumption for displays is described. The method may include receiving image data comprising a plurality of color components, generating a histogram for each of the plurality of color components, and adjusting each of a plurality of light sources based on the histograms. The plurality of light sources may correspond to the plurality of color components. Other embodiments are described and claimed.

Three-Dimensional Memory Device Including Wrap Around Word Lines And Methods Of Forming The Same

US Patent:
2021035, Nov 18, 2021
Filed:
May 18, 2020
Appl. No.:
16/877328
Inventors:
- Addison TX, US
Rahul SHARANGPANI - Fremont CA, US
Raghuveer S. MAKALA - Campbell CA, US
Fei ZHOU - San Jose CA, US
Yanli ZHANG - San Jose CA, US
International Classification:
H01L 27/11582
H01L 27/11565
H01L 27/1157
H01L 27/11543
H01L 27/11524
H01L 27/11556
H01L 27/11519
Abstract:
A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening through the alternating stack, forming lateral recesses at levels of the sacrificial material layers around the memory opening, forming a vertical stack of discrete clam-shaped semiconductor liners in the lateral recesses, replacing the vertical stack of discrete clam-shaped semiconductor liners with a vertical stack of inner clam-shaped metallic liners, forming a vertical stack of discrete charge storage elements on the vertical sack of inner clam-shaped metallic liners, forming a tunneling dielectric layer and a vertical semiconductor channel over the vertical stack of discrete charge storage elements and the vertical stack of inner clam-shaped metallic liners, and replacing each of the sacrificial material layers with an electrically conductive layer.

Three-Dimensional Memory Device With Drain-Select-Level Isolation Structures And Method Of Making The Same

US Patent:
2020025, Aug 6, 2020
Filed:
Apr 18, 2019
Appl. No.:
16/388054
Inventors:
- Addison TX, US
Makoto KOTO - Yokkaichi, JP
Sayako NAGAMINE - Yokkaichi, JP
Ching-Huang LU - Fremont CA, US
Wei ZHAO - San Jose CA, US
Yanli ZHANG - San Jose CA, US
James KAI - Santa Clara CA, US
International Classification:
H01L 27/11582
H01L 27/11519
H01L 27/11556
H01L 27/11565
H01L 21/762
Abstract:
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory pillar structures extending through the alternating stack. Each of the memory pillar structures includes a respective memory film and a respective vertical semiconductor channel Dielectric cores contact an inner sidewall of a respective one of the vertical semiconductor channels. A drain-select-level isolation structure laterally extends along a first horizontal direction and contacts straight sidewalls of the dielectric cores at a respective two-dimensional flat interface. The memory pillar structures may be formed on-pitch as a two-dimensional periodic array, and themay drain-select-level isolation structure may cut through upper portions of the memory pillar structures to minimize areas occupied by the drain-select-level isolation structure. maymay

Possible Relatives

David Zhang  Dawei Zhang  Dazhi Zhang  De K Zhang  Da Q Zhang  Dachuan Zhang  Daijun Zhang  Yanli Li  Yanli Chen 

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