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Yizheng Zhou, 498455 Pathos Ct, San Diego, CA 92129

Yizheng Zhou Phones & Addresses

8455 Pathos Ct, San Diego, CA 92129    216-9520012   

Amherst, MA   

Poway, CA   

Raleigh, NC   

Dorchester, MA   

8455 Pathos Ct, San Diego, CA 92129   

Mentions for Yizheng Zhou

Yizheng Zhou resumes & CV records

Resumes

Yizheng Zhou Photo 5

Software Engineer

Location:
San Diego, CA
Industry:
Telecommunications
Work:
Qualcomm Innovation Center Inc
Software Engineer
Education:
University of Massachusetts Amherst 2002 - 2008
Doctorates, Doctor of Philosophy, Computer Engineering
Skills:
Embedded Systems, Software Design, Algorithms, Soc, Mobile Devices, Processors, Networking, Architecture
Languages:
English
Yizheng Zhou Photo 6

Yizheng Zhou

Publications & IP owners

Us Patents

System And Method Of Controlling Power In An Electronic Device

US Patent:
2011017, Jul 14, 2011
Filed:
Jul 29, 2010
Appl. No.:
12/845974
Inventors:
NORMAN S. GARGASH - San Diego CA, US
Brian J. Salsbery - San Diego CA, US
Mark Guzzi - San Diego CA, US
Chris Barrett - San Diego CA, US
Praveen Chidambaram - San Diego CA, US
Yizheng Zhou - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 9/46
US Classification:
718104
Abstract:
A method of utilizing a node power architecture (NPA) system, the method includes receiving a request to create a client, determining whether a resource is compatible with the request, and returning a client handle when the resource is compatible with the request.

Distributed Resource Management In A Portable Computing Device

US Patent:
2012022, Sep 6, 2012
Filed:
Sep 2, 2011
Appl. No.:
13/225152
Inventors:
Norman S. GARGASH - Boulder CO, US
Vinod Vijayarajan - Boulder CO, US
Yizheng Zhou - San Diego CA, US
International Classification:
G06F 9/50
US Classification:
718104
Abstract:
In a portable computing device having a node-based resource architecture, a first or distributed node controlled by a first processor but corresponding to a second or native node controlled by a second processor is used to indirectly access a resource of the second node. In a resource graph defining the architecture each node represents an encapsulation of functionality of one or more resources, each edge represents a client request, and adjacent nodes represent resource dependencies. Resources defined by a first graph are controlled by the first processor but not the second processor, while resources defined by a second graph are controlled by the second processor but not the first processor. A client request on the first node may be received from a client under control of the first processor. Then, a client request may be issued on the second node in response to the client request on the first node.

Active And Stall Cycle Based Dynamic Scaling Of Processor Frequency And Bus Bandwidth

US Patent:
2017027, Sep 28, 2017
Filed:
Mar 28, 2016
Appl. No.:
15/082863
Inventors:
- San Diego CA, US
Yizheng Zhou - San Diego CA, US
International Classification:
G06F 13/24
G06F 13/42
Abstract:
Techniques are described in which to determine as separate values the active time and the stall time of a processing unit at different operating frequencies of the processing unit and bus bandwidths of a bus that interconnects the processing unit to system memory. The techniques may adjust the operating frequency of the processing unit and/or bus bandwidth based on the determined active times and stall times.

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