BackgroundCheck.run
Search For

Yong Hui Jiang, 6141 Putting Green Ln, Orange, CT 06477

Known as:
Yong H Jiang Ying H Jiang Yonghui Jiang Yin G Jiang Tonghui Jiang Jin G Yang Jing Yang Jiahg Yong-Hui Jiang Yong-Hui
Related to:
Xue Yang 54

Yong Jiang Phones & Addresses

Orange, CT   

North Haven, CT   

San Francisco, CA   

Chapel Hill, NC   

2907 Chiswell St, Houston, TX 77025    713-3499482   

Durham, NC   

Ann Arbor, MI   

Get Report
Control this profile

Mentions for Yong Hui Jiang

Career records & work history

Medicine Doctors

Yong Mei Jiang

Specialties:
Internal Medicine
Education:
Medical School
University of Colorado School of Medicine at Denver
Graduated: 2002
Conditions:
Acute Myocardial Infarction (AMI), Acute Pancreatitis, Acute Renal Failure, Alcohol Dependence, Anemia, Angina Pectoris, Atherosclerosis, Atrial Fibrillation and Atrial Flutter, Bacterial Pneumonia, Calculus of the Urinary System, Cardiac Arrhythmia, Cholelethiasis or Cholecystitis, Chronic Bronchitis, Chronic Renal Disease, Cirrhosis, Dementia, Depressive Disorders, Diverticulitis, Epilepsy, Esophagitis, Fractures, Dislocations, Derangement, and Sprains, Gastritis and Duodenitis, Gastrointestinal Hemorrhage, Heart Failure, Hemorrhagic stroke, HIV Infection, Inflammatory Bowel Disease (IBD), Influenza, Intervertebral Disc Degeneration, Intestinal Obstruction, Intracranial Injury, Iron Deficiency Anemia, Ischemic Heart Disease, Ischemic Stroke, Malignant Neoplasm of Female Breast, Multiple Sclerosis (MS), Obstructive Sleep Apnea, Osteoarthritis, Osteomyelitis, Parkinson's Disease, Peptic Ulcer Disease, Peripheral Nerve Disorders, Pneumonia, Poisoning by Drugs, Meds, or Biological Substances, Pulmonary Embolism, Rheumatoid Arthritis, Septicemia, Skin and Subcutaneous Infections, Spinal Stenosis, Transient Cerebral Ischemia, Urinary Tract Infection (UT), Valvular Heart Disease, Venous Embolism and Thrombosis, Abdominal Aortic Aneurysm, Acute Bronchitis, Acute Pharyngitis, Acute Sinusitis, Acute Upper Respiratory Tract Infections, Anal or Rectal Abscess, Anxiety Phobic Disorders, Arterial Thromboembolic Disease, Atopic Dermatitis, Benign Paroxysmal Positional Vertigo, Benign Thyroid Diseases, Bronchial Asthma, Cardiomyopathy, Carditis, Chickenpox, Chronic Pancreatitis, Conduction Disorders, Congenital Anomalies of the Heart, Constipation, Dermatitis, Diabetes Mellitus (DM), Disorders of Lipoid Metabolism, Diverticulosis, Endocarditis, Gout, Hemolytic Anemia, Herpes Zoster, Hypertension (HTN), Hyperthyroidism, Hypothyroidism, Infectious Liver Disease, Inguinal Hernia, Internal Derangement of Knee, Irritable Bowel Syndrome (IBS), Ischemic Bowel Disease, Meningitis, Migraine Headache, Mitral Valvular Disease, Myasthenia Gravis (MG), Orbital Infection, Osteoporosis, Otitis Media, Overweight and Obesity, Paroxysmal Supreventricular Tachycardia (PSVT), Pericardidtis, Psoriasis, Sarcoidosis, Scoliosis or Kyphoscoliosis, Sickle-Cell Disease, Substance Abuse and/or Dependency, Systemic Lupus Erythematosus, Thyroid Cancer, Urinary Incontinence, Varicose Veins, Ventral Hernia
Description:
Dr. Jiang graduated from the University of Colorado School of Medicine at Denver in 2002. She works in Greenwood Village, CO and specializes in Internal Medicine. Dr. Jiang is affiliated with Kindred Hospital Aurora, Littleton Adventist Hospital and Sky Ridge Medical Center.
Yong Jiang Photo 1

Yong Hui Jiang, Houston TX

Specialties:
Medical Genetics
Clinical Genetics
M.D.
Pediatrics
Work:
Genetics Clinic
6701 Fannin St, Houston, TX 77030Private Diagnostic Clinic
2301 Erwin Rd, Durham, NC 27710Baylor College of Medicine
6620 Main St, Houston, TX 77030
Education:
Shanghai First Medical College (1987)

Yong Jiang resumes & CV records

Resumes

Yong Jiang Photo 35

Yong Jiang

Yong Jiang Photo 36

Yong Jiang

Yong Jiang Photo 37

Senior Transmission Utilization Engineer At Midwest Iso

Location:
United States

Publications & IP owners

Us Patents

Network Interface With Double Data Rate And Delay Locked Loop

US Patent:
6920552, Jul 19, 2005
Filed:
Feb 27, 2002
Appl. No.:
10/083291
Inventors:
Jonathan Lin - Fremont CA, US
Yong Jiang - Fremont CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G03F007/38
US Classification:
713 1
Abstract:
A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e. g. , from internal device logic) is output from the data I/O device to the at least one port.

Network Interface Using Programmable Delay And Frequency Doubler

US Patent:
6934866, Aug 23, 2005
Filed:
Mar 18, 2002
Appl. No.:
10/098337
Inventors:
Jonathan Lin - Fremont CA, US
Yong Jiang - Fremont CA, US
Assignee:
Broadcom Corporaton - Irvine CA
International Classification:
G06F001/12
US Classification:
713401
Abstract:
A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal with a frequency double that of the input signal. The data I/O device is configured to output data to the at least one port based on a reference clock signal. The variable delay circuit is located between the data I/O device and at least one port. An external clock signal received at the input is input into the frequency doubler. The output signal of the frequency doubler is applied to the data I/O device as the reference clock signal, and the output data is delayed by the variable delay circuit.

Network Interface Using Programmable Delay And Frequency Doubler

US Patent:
7024576, Apr 4, 2006
Filed:
Jul 14, 2005
Appl. No.:
11/180628
Inventors:
Jonathan Lin - Fremont CA, US
Yong Jiang - Fremont CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G04F 8/00
US Classification:
713400
Abstract:
A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal with a frequency double that of the input signal. The data I/O device is configured to output data to the at least one port based on a reference clock signal. The variable delay circuit is located between the data I/O device and at least one port. An external clock signal received at the input is input into the frequency doubler. The output signal of the frequency doubler is applied to the data I/O device as the reference clock signal, and the output data is delayed by the variable delay circuit.

Network Interface With Double Data Rate And Delay Locked Loop

US Patent:
7134010, Nov 7, 2006
Filed:
Jun 10, 2005
Appl. No.:
11/149182
Inventors:
Jonathan Lin - Fremont CA, US
Yong Jiang - Fremont CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G03F 7/38
US Classification:
713 1
Abstract:
A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e. g. , from internal device logic) is output from the data I/O device to the at least one port.

Network Interface With Double Date Rate And Delay Locked Loop

US Patent:
7308568, Dec 11, 2007
Filed:
Oct 16, 2006
Appl. No.:
11/580956
Inventors:
Jonathan Lin - Fremont CA, US
Yong Jiang - Fremont CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G03F 7/38
US Classification:
713 1
Abstract:
A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e. g. , from internal device logic) is output from the data I/O device to the at least one port.

Method And Apparatus For Glitch-Free Control Of A Delay-Locked Loop In A Network Device

US Patent:
7348820, Mar 25, 2008
Filed:
Aug 29, 2006
Appl. No.:
11/511309
Inventors:
Yong H. Jiang - Fremont CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03L 7/06
US Classification:
327158, 327149
Abstract:
A method of controlling a delay-locked loop (DLL) module is disclosed. The method includes the steps of receiving a clock signal, comparing the received clock signal with a reference clock signal to determine whether a required phase difference between the signals is within specified tolerances, producing a correction signal when the required phase difference between the received clock and reference clock signals is not within the specified tolerances, utilizing the correction signal to change a delay setting and forwarding the correction signal to slave DLL modules in communication with the DLL module. The comparing, producing, utilizing and forwarding steps are performed only after a period of time has elapsed from a prior incidence of the comparing, producing, utilizing and forwarding steps, where the period of time is sufficient to allow the DLL to settle and no extraneous results are produced.

Possible Relatives

Cynthia Jiang  David Q Jiang  Daniel X Jiang  Danny P Jiang  Dennis Jiang  Dian Jiang  Dongyan Jiang  Yong I Johnson  Yong S White  Yong C Stanley 

NOTICE: You may not use BackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. BackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.