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Ying Ji, 48Palo Alto, CA

Known as:
Yu Ji Yong Ji Yzng Ji
Related to:
Michael Xiong Song 62 Lijun J Song 65

Ying Ji Phones & Addresses

Palo Alto, CA   

Stateline, NV   

Fremont, CA   

660 Montara Ter, Sunnyvale, CA 94085    408-8309472   

Morrisville, NC   

New York, NY   

Alameda, CA   

1090 Sunnyvale Saratoga Rd Apt, Sunnyvale, CA 94087    408-4810482   

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Ying Ji resumes & CV records

Resumes

Ying Ji Photo 25

Ying Ji

Location:
Palo Alto, CA
Industry:
Financial Services
Work:
Wells Fargo Jun 2007 - Jan 2013
Risk Management Consultant Rti International Aug 2001 - Jul 2005
Research Assistant
Education:
Duke University 1999 - 2001
Master of Science, Masters, Public Policy Central University of Finance and Economics 1994 - 1998
Bachelors, Bachelor of Science, Economics
Skills:
Microsoft Office, Microsoft Excel, Microsoft Word, Powerpoint, English, Research, Windows, Outlook
Ying Ji Photo 26

Ying (Mandy) Ji

Location:
San Francisco Bay Area
Industry:
Semiconductors
Ying Ji Photo 27

Ying Ji

Location:
United States

Publications & IP owners

Us Patents

Distributed On-Chip Decoupling Apparatus And Method Using Package Interconnect

US Patent:
2013032, Dec 5, 2013
Filed:
May 28, 2013
Appl. No.:
13/903323
Inventors:
Ling Yang - San Jose CA, US
Chanh Tran - San Jose CA, US
Ying Ji - San Jose CA, US
Assignee:
Rambus Inc. - Sunnyvale CA
International Classification:
H01L 23/48
H01L 21/768
US Classification:
257774, 438637
Abstract:
An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.

Distributed On-Chip Decoupling Apparatus And Method Using Package Interconnect

US Patent:
2017009, Apr 6, 2017
Filed:
Oct 3, 2016
Appl. No.:
15/284295
Inventors:
- Sunnyvale CA, US
Ling Yang - San Jose CA, US
Chanh Tran - San Jose CA, US
Ying Ji - San Jose CA, US
International Classification:
H01L 23/48
H01L 25/065
H01L 21/768
H01L 23/528
Abstract:
An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.

Distributed On-Chip Decoupling Apparatus And Method Using Package Interconnect

US Patent:
2015022, Aug 6, 2015
Filed:
Apr 9, 2015
Appl. No.:
14/683073
Inventors:
- Sunnyvale CA, US
Ling Yang - San Jose CA, US
Chanh Tran - San Jose CA, US
Ying Ji - San Jose CA, US
International Classification:
H01L 23/528
H03K 5/1252
H01L 23/48
Abstract:
An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.

Possible Relatives

Daniel D Ji  Douglas K Ji  Eunjung Ji  Guo Ji  Hae K Ji  Henry H Ji  Hongbin Ji  Ying F Lam  Ying H Lee  Ying K Leung 

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