Yu Zhu, 44Edmond, OK

6856210, Feb 15, 2005

Apr 27, 2001

09/842768

Yu Zhu - Pine Brook NJ, US
Eiji Suematsu - Nara, JP

Sharp Kabushiki Kaisha - Osaka

H03H007/38
H01P003/08

333 33, 333246

A high-frequency multilayer circuit substrate having a plurality of circuit layers includes a via hole for connection between the circuit layers, a metal pad, an impedance matching transmission line, rectangular stubs and a signal transmission line. A via hole connecting portion is constructed of the via hole, the rectangular stubs and the impedance matching transmission line. A characteristic impedance of the via hole connecting portion is matched to a characteristic impedance of the signal transmission line by adjusting widths and lengths of the impedance matching transmission line and the rectangular stubs. Thereby, the reflection of the signal wave in the via hole connecting portion is reduced to decrease a transmission loss.

2012011, May 10, 2012

Nov 9, 2010

12/942498

Jack O. Chu - Manhasset Hills NY, US
Christos D. Dimitrakopoulos - Baldwin Place NY, US
Alfred Grill - White Plains NY, US
Timothy J. McArdle - Mahopac NY, US
Katherine L. Saenger - Ossining NY, US
Robert L. Wisnieff - Ridgefield CT, US
Yu Zhu - West Harrison NY, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

H01L 29/04
H01L 29/24
C30B 25/18

257 64, 117104, 257 77, 257E29104, 257E29004

remove impurities from an exposed surface in the ultrahigh vacuum environment. A high qualify single crystalline or polycrystalline silicon carbide film can be grown directly on the sapphire substrate by chemical vapor deposition employing a silicon-containing reactant and a carbon-containing reactant. Formation of single crystalline silicon carbide has been verified by x-ray diffraction, secondary ion mass spectroscopy, and transmission electron microscopy.

2014005, Feb 27, 2014

Sep 12, 2012

13/611893

Joseph S. Newbury - Irvington NY, US
Kenneth Parker Rodbell - Sandy Hook CT, US
Zhen Zhang - Ossining NY, US
Yu Zhu - West Harrison NY, US

International Business Machines Corporation - Armonk NY

H01L 27/12

257347, 257E27112

Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device include a semiconductor material selected from: silicon and silicon germanium; and silicide contacts to the source and drain regions of the device, wherein an interface is present between the silicide contacts and the semiconductor material, and wherein the interface has an interface roughness of less than about 5 nanometers.

2014005, Feb 27, 2014

Aug 24, 2012

13/593725

Joseph S. Newbury - Irvington NY, US
Kenneth Parker Rodbell - Sandy Hook CT, US
Zhen Zhang - Ossining NY, US
Yu Zhu - West Harrison NY, US

International Business Machines Corporation - Armonk NY

H01L 21/3205
H01L 21/336

438158, 438683, 257E21296, 257E21409

Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a cap layer-free method for forming a silicide is provided. The method includes the following steps. A semiconductor material selected from: silicon and silicon germanium is provided. At least one silicide metal is deposited on the semiconductor material. The semiconductor material and the at least one silicide metal are annealed at a temperature of from about 400 C. to about 800 C. for a duration of less than or equal to about 10 milliseconds to form the silicide. A FET device and a method for fabricating a FET device are also provided.

2018009, Apr 5, 2018

Apr 18, 2017

15/490414

- ARMONK NY, US
Kevin K. Chan - Staten Island NY, US
John Rozen - Hastings on Hudson NY, US
Jeng-Bang Yau - Yorktown Heights NY, US
Yu Zhu - Rye Brook NY, US

H01L 21/8234
H01L 29/66
H01L 21/02
H01L 21/18
H01L 21/3215

A method for forming a semiconductor device includes forming a III-V semiconductor substrate and forming a gate structure on the III-V semiconductor substrate. The method also includes forming a thin spacer surrounding the gate structure and forming a source/drain junction with a first doped III-V material at an upper surface of the III-V semiconductor substrate. The method also includes oxidizing a surface the source/drain forming an oxidation layer; removing natural oxides from the oxidation layer on a surface of the source/drain to expose ions of the first doped III-V material at least at a surface of the source/drain. The method further includes applying a second doping to the source/drain to increase a doping concentration of the first doped III-V material, forming metal contacts at least at the second doped surface of the source/drain; and then annealing the contact.