Yujie LiuSunnyvale, CA

2008027, Nov 6, 2008

Oct 10, 2007

11/870212

Ashok Kumar Kapoor - Palo Alto CA, US
Madhukar B. Vora - Los Gatos CA, US
Weimin Zhang - San Jose CA, US
Sachin R. Sonkusale - Campbell CA, US
Yujie Liu - Sunnyvale CA, US

H01L 29/808
H01L 21/337
H01L 29/00

257190, 257268, 257513, 438196, 257E21446, 257E29312, 257E29001

Junction field effect transistors (JFET) formed in substrates containing germanium. JFETs having polycrystalline semiconductor surface contacts with self-aligned silicide formed thereon and self-aligned source, drain and gate regions formed by thermal drive-in of impurities from surface contacts into the substrate, and implanted link regions. Others have a polycrystalline semiconductor gate surface contact and metal back gate, source and drain contacts and a metal surface contact to the gate surface contact with implanted source and drains and a self-aligned gate region. JFETs having a polycrystalline semiconductor gate surface contact and metal back gate, source and drain contacts and a metal surface contact to the gate surface contact with implanted source and drains and a self-aligned gate region and silicide formed on the top of the source, drain and back gate contacts and on top of the gate polycrystalline semiconductor gate contact to which the metal surface contacts make electrical contact.

2016025, Sep 8, 2016

May 16, 2016

15/156110

- Redwood City CA, US
Yosef Lev - New York NY, US
Yujie Liu - Bethlehem PA, US
Victor M. Luchangco - Cambridge MA, US
Mark S. Moir - Wellington, NZ

G06F 9/46
G06F 9/50

Transactional reader-writer locks may leverage available hardware transactional memory (HTM) to simplify the procedures of the reader-writer lock algorithm and to eliminate a requirement for type stable memory An HTM-based reader-writer lock may include an ordered list of client-provided nodes, each of which represents a thread that holds (or desires to acquire) the lock, and a tail pointer. The locking and unlocking procedures invoked by readers and writers may access the tail pointer or particular ones of the nodes in the list using various combinations of transactions and non-transactional accesses to insert nodes into the list or to remove nodes from the list. A reader or writer that owns a node at the head of the list (or a reader whose node is preceded in the list only by other readers' nodes) may access a critical section of code or shared resource.

2015033, Nov 19, 2015

Jul 24, 2015

14/808122

- Kuwana, JP
Lucian Shifren - San Jose CA, US
Pushkar Ranade - Los Gatos CA, US
Yujie Liu - San Jose CA, US
Sung Hwan Kim - San Jose CA, US
Lingquan Wang - Irvine CA, US
Dalong Zhao - San Jose CA, US
Teymur Bakhishev - San Jose CA, US
Thomas Hoffmann - Los Gatos CA, US
Sameer Pradhan - Campbell CA, US
Michael Duane - Santa Clara CA, US

H01L 29/66
H01L 29/10
H01L 29/08

A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.

2015006, Mar 5, 2015

Nov 6, 2014

14/534595

- Los Gatos CA, US
Lucian Shifren - San Jose CA, US
Pushkar Ranade - Los Gatos CA, US
Yujie Liu - San Jose CA, US
Sung Hwan Kim - San Jose CA, US
Lingquan Wang - Irvine CA, US
Dalong Zhao - San Jose CA, US
Teymur Bakhishev - San Jose CA, US
Thomas Hoffmann - Los Gatos CA, US
Sameer Pradhan - Campbell CA, US
Michael Duane - Santa Clara CA, US

H01L 29/78

257344

A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.

2014025, Sep 11, 2014

Mar 5, 2013

13/784965

- Redwood City CA, US
Yosef Lev - New York NY, US
Yujie Liu - Bethlehem PA, US
Victor M. Luchangco - Cambridge MA, US
Mark S. Moir - Wellington, NZ

ORACLE INTERNATIONAL CORPORATION - Redwood City CA

G06F 12/14

711152

Transactional reader-writer locks may leverage available hardware transactional memory (HTM) to simplify the procedures of the reader-writer lock algorithm and to eliminate a requirement for type stable memory An HTM-based reader-writer lock may include an ordered list of client-provided nodes, each of which represents a thread that holds (or desires to acquire) the lock, and a tail pointer. The locking and unlocking procedures invoked by readers and writers may access the tail pointer or particular ones of the nodes in the list using various combinations of transactions and non-transactional accesses to insert nodes into the list or to remove nodes from the list. A reader or writer that owns a node at the head of the list (or a reader whose node is preceded in the list only by other readers' nodes) may access a critical section of code or shared resource.

2014008, Mar 27, 2014

Sep 5, 2013

14/019187

- Los Gatos CA, US
Lucian Shifren - San Jose CA, US
Scott E. Thompson - Gainesville FL, US
Pushkar Ranade - Los Gatos CA, US
Jing Wang - San Jose CA, US
Paul E. Gregory - Palo Alto CA, US
Sachin R. Sonkusale - Los Gatos CA, US
Lance Scudder - Sunnyvale CA, US
Dalong Zhao - San Jose CA, US
Teymur Bakhishev - San Jose CA, US
Yujie Liu - San Jose CA, US
Lingquan Wang - Irvine CA, US
Weimin Zhang - San Jose CA, US
Sameer Pradhan - San Jose CA, US
Michael Duane - San Carlos CA, US
Sung Hwan Kim - San Jose CA, US

SuVolta, Inc. - Los Gatos CA

H01L 29/78

257402

A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure.