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Yun F Li, 872225 4Th Ave UNIT 304, Seattle, WA 98121

Known as:
Fan Li Yun Li F Yun
Related to:
Li Shi 55 Fucheng Li 34

Yun Li Phones & Addresses

Waukegan, IL   

San Francisco, CA   

Oroville, CA   

Work

Company: Boston university Jul 2012 Position: Postdoctoral fellow

Education

School / High School: University of Michigan 2007 Specialities: Ph.D. in Statistics

Skills

C/C++ • SQL • R • Matlab • SAS • Python
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Mentions for Yun F Li

Career records & work history

Medicine Doctors

Yun Y. Li

Specialties:
Cardiovascular Disease
Work:
OhioHealth Heart & Vascular Physicians
171 Morey Dr STE C, Marysville, OH 43040
937-6444441 (phone) 937-6420302 (fax)
Site
Education:
Medical School
Henan Med Univ, Zhengzhou City, Henan, China
Graduated: 1985
Procedures:
Cardiac Stress Test, Cardioversion, Echocardiogram, Continuous EKG, Electrocardiogram (EKG or ECG), Pacemaker and Defibrillator Procedures
Conditions:
Heart Failure, Acute Myocardial Infarction (AMI), Angina Pectoris, Aortic Aneurism, Aortic Regurgitation, Aortic Valvular Disease, Atrial Fibrillation and Atrial Flutter, Bronchial Asthma, Cardiac Arrhythmia, Cardiomyopathy, Chronic Bronchitis, Conduction Disorders, Congenital Anomalies of the Heart, Diabetes Mellitus (DM), Disorders of Lipoid Metabolism, Endocarditis, Hypertension (HTN), Ischemic Heart Disease, Ischemic Stroke, Lyme Disease, Mitral Valvular Disease, Obstructive Sleep Apnea, Overweight and Obesity, Paroxysmal Supreventricular Tachycardia (PSVT), Pulmonary Embolism, Skin and Subcutaneous Infections, Valvular Heart Disease, Venous Embolism and Thrombosis
Languages:
Chinese, English, Spanish
Description:
Dr. Li graduated from the Henan Med Univ, Zhengzhou City, Henan, China in 1985. Dr. Li works in Marysville, OH and specializes in Cardiovascular Disease. Dr. Li is affiliated with Memorial Hospital and OhioHealth Doctors Hospital.

Yun Li resumes & CV records

Resumes

Yun Li Photo 39

Yun Li - Boston, MA

Work:
Boston University Jul 2012 to 2000
Postdoctoral Fellow Department of Statistics, University of Michigan - Ann Arbor, MI Sep 2007 to Apr 2012
Research Assistant CardioDx, Inc - Palo Alto, CA Jun 2009 to Aug 2009
Intern Cyclotron Institute, Texas A&M University - College Station, TX May 2005 to Aug 2007
Research Assistant
Education:
University of Michigan 2007 to 2012
Ph.D. in Statistics Texas A&M University 2007
M.S. in Physics University of Science and Technology of China 2001
B.S. in Physics
Skills:
C/C++, SQL, R, Matlab, SAS, Python

Publications & IP owners

Wikipedia

Yun Li Photo 40

Li Yun

Li Yun () (died 887), imperial princely title Prince of Xiang (), was a pretender to the throne of the Chinese dynasty Tang Dynasty, who briefly, under the ...
Yun Li Photo 41

Li Yun (Water Margin)

Li Yun is a fictional character in the Water Margin, one of the Four Great Classical Novels of Chinese literature. He ranks 97th of the 108 Liangshan heroes and 61st

Us Patents

Managing Queues Of A Memory Sub-System

US Patent:
2022040, Dec 22, 2022
Filed:
Mar 10, 2020
Appl. No.:
16/954156
Inventors:
- Boise ID, US
Jing Sang Liu - Shanghai, CN
Yun Li - Fremont CA, US
James P. Crowley - Longmont CO, US
International Classification:
G06F 3/06
Abstract:
Methods, systems, and devices for managing queues of a memory sub-system are described. A first command can be assigned to a first queue of a memory die of a memory sub-system. The first queue can be is associated with a first priority level and the memory die can include a second queue associated with a second priority level different from the first priority level. The second queue can include a second command, where the first command and the second command are each associated with a respective operation to be performed on the memory sub-system. In some examples, the first command can be issued before the second command based on the first and second priority levels.

Command Batching For A Memory Sub-System

US Patent:
2022037, Nov 24, 2022
Filed:
Jul 8, 2022
Appl. No.:
17/860999
Inventors:
- Boise ID, US
Yun Li - Fremont CA, US
Scheheresade Virani - Frisco TX, US
Ning Zhao - Milpitas CA, US
Tom Victor Maria Geukens - Longmont CO, US
International Classification:
G06F 3/06
Abstract:
Methods, systems, and devices for command batching for a memory sub-system are described. A memory sub-system can receive a plurality of commands for a plurality of transfer units of a memory sub-system and generate a list of the plurality of transfer units that includes pointers between the plurality of transfer units. The memory sub-system can store at least one pointer of the list in a shared memory that is shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list. The memory sub-system can send an indicator of a first transfer unit of the list based on storing the at least one pointer in the shared memory and retrieve the plurality of transfer units from the shared memory based on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.

Hardware-Based Coherency Checking Techniques

US Patent:
2021040, Dec 30, 2021
Filed:
Sep 8, 2021
Appl. No.:
17/469342
Inventors:
- Boise ID, US
Yun Li - Fremont CA, US
International Classification:
G06F 12/0831
G06F 12/02
Abstract:
Methods, systems, and devices for hardware-based coherency checking techniques are described. A memory sub-system with hardware-based coherency checking can include a coherency block that maintains a coherency lock and releases coherency upon completion of a write command. The coherency block can perform operations to lock coherency associated with the write command, monitor for completion of the write to the memory device(s), release the coherency lock, and update one or more records used to monitor coherency associated with the write command. A coherency command and coherency status can be provided through a dedicated hardware bridge, such as a bridge through a level-zero cache coupled with the coherency hardware.

Dynamic Selection Of Cores For Processing Responses

US Patent:
2021029, Sep 23, 2021
Filed:
Mar 18, 2020
Appl. No.:
16/822916
Inventors:
- Boise ID, US
Yun Li - Fremont CA, US
Scheheresade Virani - Frisco TX, US
John Paul Traver - Boise ID, US
Ning Zhao - Milpitas CA, US
International Classification:
G06F 3/06
G06F 9/50
Abstract:
Methods, systems, and devices for the dynamic selection of cores for processing responses are described. A memory sub-system can receive, from a host system, a read command to retrieve data. The memory sub-system can include a first core and a second core. The first core can process the read command based on receiving the read command. The first core can identify the second core for processing a read response associated with the read command. The first core can issue an internal command to retrieve the data from a memory device of the memory sub-system. The internal command can include an indication of the second core selected to process the read response.

Command Batching For A Memory Sub-System

US Patent:
2021027, Sep 9, 2021
Filed:
Mar 4, 2020
Appl. No.:
16/809360
Inventors:
- Boise ID, US
Yun Li - Fremont CA, US
Scheheresade Virani - Frisco TX, US
Ning Zhao - Milpitas CA, US
Tom Victor Maria Geukens - Longmont CO, US
International Classification:
G06F 3/06
Abstract:
Methods, systems, and devices for command batching for a memory sub-system are described. A memory sub-system can receive a plurality of commands for a plurality of transfer units of a memory sub-system and generate a list of the plurality of transfer units that includes pointers between the plurality of transfer units. The memory sub-system can store at least one pointer of the list in a shared memory that is shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list. The memory sub-system can send an indicator of a first transfer unit of the list based on storing the at least one pointer in the shared memory and retrieve the plurality of transfer units from the shared memory based on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.

Hardware-Based Coherency Checking Techniques

US Patent:
2021027, Sep 9, 2021
Filed:
Mar 4, 2020
Appl. No.:
16/809036
Inventors:
- Boise ID, US
Yun Li - Fremont CA, US
International Classification:
G06F 12/0831
G06F 12/02
Abstract:
Methods, systems, and devices for hardware-based coherency checking techniques are described. A memory sub-system with hardware-based coherency checking can include a coherency block that maintains a coherency lock and releases coherency upon completion of a write command. The coherency block can perform operations to lock coherency associated with the write command, monitor for completion of the write to the memory device(s), release the coherency lock, and update one or more records used to monitor coherency associated with the write command. A coherency command and coherency status can be provided through a dedicated hardware bridge, such as a bridge through a level-zero cache coupled with the coherency hardware.

Identifying Asynchronous Power Loss

US Patent:
2019037, Dec 5, 2019
Filed:
Aug 19, 2019
Appl. No.:
16/544190
Inventors:
- Boise ID, US
Ashutosh Malshe - Fremont CA, US
Violante Moschiano - Avezzano, IT
Peter Feeley - Boise ID, US
Gary F. Besinga - Boise ID, US
Sampath K. Ratnam - Boise ID, US
Walter Di-Francesco - Silvi, IT
Yun Li - San Jose CA, US
Kishore Kumar Muchherla - Fremont CA, US
Assignee:
MICRON TECHNOLOGY, INC. - BOISE ID
International Classification:
G06F 11/07
G06F 3/06
Abstract:
Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.

Identifying Asynchronous Power Loss

US Patent:
2019007, Mar 7, 2019
Filed:
Nov 2, 2018
Appl. No.:
16/178963
Inventors:
- BOISE ID, US
Ashutosh Malshe - Fremont CA, US
Violante Moschiano - Avezzano, IT
Peter Feeley - Boise ID, US
Gary F. Besinga - Boise ID, US
Sampath K. Ratnam - Boise ID, US
Walter Di-Francesco - Silvi, IT
Yun Li - San Jose CA, US
Kishore Kumar Muchherla - Fremont CA, US
Assignee:
MICRON TECHNOLOGY, INC. - BOISE ID
International Classification:
G06F 11/07
G06F 3/06
Abstract:
Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.

Isbn (Books And Publications)

Parallel Processing In A Control Systems Environment

Author:
Yun Li
ISBN #:
0136515304

Possible Relatives

Cynthia M Li  David Li  Dawei Li  Dayu W Li  De Li  Dean Li  Da Li  Yun R Jun  Yun J Lee  Yun C Leung 

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