Yusuke T Tajima, 804 Russell Rd, Acton, MA 01720

8224264, Jul 17, 2012

Nov 13, 2009

12/618192

Yusuke Tajima - Acton MA, US
Mark A. Royer - Billerica MA, US
James A. Sozanski - Bolton MA, US

Auriga Measurement Systems, LLC - Chelmsford MA

H03C 1/52
H01Q 11/12
H04B 1/04

455108, 4551272

A power supply stage includes a digital signal generation means to generate n bit digital signal, a selection means for power supply voltages in dependence on n bit digital signal and an adjusting means for receiving the selected power supply voltage and the envelope signal and adapted to generate an adjusted selected power supply voltage tracking the envelope signal.

8289085, Oct 16, 2012

Dec 16, 2010

12/970240

Yusuke Tajima - Acton MA, US
John Muir - North Chelmsford MA, US

Auriga Measurement Systems, LLC - Chelmsford MA

H03F 3/04

330301, 330124 R

An amplifier circuit includes a pair of amplifying devices, a first balun coupled between an input port of the amplifier circuit and RF input ports of the pair of amplifying devices and a second balun coupled between RF output ports of the pair of amplifying devices and an output port of the amplifier circuit wherein the first and second baluns are configured such that the amplifier circuit operates under open condition for signals at a second harmonic frequency even when the second harmonic frequency is within an operating frequency band of a fundamental frequency of the amplifier circuit. In one embodiment, the amplifier circuit includes a bypass circuit which selectively couples balun ports to ground such that in response to a first control signal, the amplifier circuit operates in an amplifying mode and in response to a second control signal, the amplifier circuit operates in a bypass mode.

8368451, Feb 5, 2013

Mar 31, 2011

13/077096

Steven A. Mulawski - Tyngsborough MA, US
Yusuke Tajima - Acton MA, US

Auriga Measurement Systems, LLC - Chelmsford MA

H01P 1/22

327308, 333 81 R

A radio frequency (RF) switch circuit includes switching devices coupled at a common node and a floating control signal circuit (CSS) coupled to the control electrodes of the switching devices and the common node and configured to isolate RF signals from the CSS and configured to provide differential voltage signals to the common node and each of the control electrodes.

2013020, Aug 15, 2013

Feb 14, 2013

13/767018

Yusuke Tajima - Acton MA, US

AURIGA MEASUREMENT SYSTEMS, LLC - Chelmsford MA

H03F 3/193
H03F 3/45
H03F 3/21

330253, 330277, 330301

An envelope tracking power amplifier uses signal cancellation techniques to provide isolation between RF signals and envelope signals, without the use of filters. In this manner, the envelope tracking power amplifiers are capable of operating with envelope signals that are at or near the frequency of the corresponding RF signals. In at least one embodiment, a double balanced power amplifier is provided that includes a balanced RF input port, a balanced RF output port, and a balanced envelope input port. The balanced nature of the amplifier results in ports of the amplifier forming virtual grounds with respect to signals at other ports. In some other embodiments, a single balanced amplifier is provided that provides isolation between ports thereof.

2013024, Sep 19, 2013

Mar 7, 2013

13/788407

Yusuke Tajima - Acton MA, US
John Muir - North Chelmsford MA, US

AURIGA MEASUREMENT SYSTEMS, LLC - Chelmsford MA

H03G 3/00

330285

Circuits and techniques to linearize the operation of an RF power amplifier are described. A linearizer circuit may include a non-amplification signal path which includes a delay line and an amplification signal path which includes at least one amplifier stage. In some embodiments, the amplification signal path may include an odd number of amplification stages. The linearizer may be used to precondition an input signal of an RF power amplifier in a manner that improves the overall linearity of operation.

4660006, Apr 21, 1987

Apr 15, 1985

6/723593

Yusuke Tajima - Acton MA
Robert A. Pucel - Needham MA

Raytheon Company - Lexington MA

H03B 1914

333218

A radio frequency multiplier circuit includes a first plurality of non-linear devices, each device having an input electrode and an output electrode. The input electrode of each one of the first plurality of non-linear devices is successively interconnected via a first input coupling means to a first input terminal. The multiplier further includes a second like plurality of non-linear devices, each device having an input electrode and an output electrode. The input electrode of each one of the second plurality of non-linear devices is successively interconnected via a second input coupling means to a second input terminal. A common output coupling means is provided to interconnect the output electrode of each one of the first plurality of devices with the output electrode of a corresponding one of the second plurality of devices. The multiplier further includes means for coupling a pair of signals having a 180. degree. differential phase shift to the pair of input terminals.

5021743, Jun 4, 1991

Nov 30, 1989

7/443985

Shiou L. L. Chu - Bedford MA
Yusuke Tajima - Acton MA
Manfred J. Schindler - Newton MA

Raytheon Company - Lexington MA

H03F 360

330 54

A radio frequency matrix amplifier includes an input propagation network for successively connecting input electrodes of a first plurality of transistors. Output electrodes are successively coupled by an intermediate propagation network. The amplifier also includes a second plurality of transistors, having input electrodes successively coupled by the intermediate propagation network and output electrodes successively coupled by an output propagation network. A bias circuit for the amplifier includes an inductor connected between a last one of the second plurality of transistors and the intermediate propagation network and a plurality of capacitors disposed to connect reference electrodes of the second plurality of transistors to a reference potential. With this arrangement stages are connected in series for D. C. potentials and in cascade for r. f.

4787686, Nov 29, 1988

Feb 17, 1987

7/044924

Yusuke Tajima - Acton MA
Toshikazu Tsukii - Santa Barbara CA

Raytheon Company - Lexington MA

H03K 508
H03H 1124

307568

A programmable attenuator includes a plurality of field effect transistors (FETS) arranged together to provide an attenuation network. Each one of the FETS has a plurality of cell portions, each cell portion having drain, gate and source regions, the source and drain regions of the cell portions being connected in parallel. A first selected portion of the gate regions of each one of said FETS is connected to a gate electrode. A second selected remaining portion of the gate regions of each one of the FETS has the gate regions thereof physically isolated from the gate electrode. A signal fed to the gate electrode of each FET is distributed to the connected gate regions of each field effect transistor. In response to such signal, the total drain-source resistance of such FET is changed between a predetermined low value and a predetermined high value, with the resistance of the predetermined high value being determined, in part, by the number of such isolated gate regions.