Yan Q TangMonterey Park, CA

6459428, Oct 1, 2002

Oct 3, 2001

09/970077

Wayne Eric Burk - San Jose CA
Yan Y. Tang - Mountain View CA
Michael G. Lavelle - Saratoga CA
Philip C. Leung - Fremont CA
Michael F. Deering - Los Altos CA
Ranjit S. Oberoi - Saratoga CA

Sun Microsystems, Inc. - Palo Alto CA

G06T 1500

345419

A graphics system configured to perform programmable filtering of samples to generate pixel values. The graphics system comprises a frame buffer, an accelerator unit and a video output processor. The accelerator unit receives graphics primitives, renders samples for the graphics primitives, and stores the rendered samples into a sample area of the frame buffer. The accelerator unit subsequently reads the samples from the sample area of the frame buffer, and filters the samples with a programmable filter having a programmable support region. The resulting pixel values are stored in a pixel area of the frame buffer. The video output processor reads the pixel values from the pixel area and converts the pixel values into a video signal which is provided to a video output port.

6720969, Apr 13, 2004

May 18, 2001

09/861172

Michael G. Lavelle - Saratoga CA
Ewa M. Kubalska - San Jose CA
Yan Yan Tang - Mountain View CA

Sun Microsystems, Inc. - Santa Clara CA

G09G 536

345557, 345537, 345531, 711122, 711131

An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.

6778179, Aug 17, 2004

Oct 3, 2001

09/970113

Michael G. Lavelle - Saratoga CA
Ewa M. Kubalska - Sun Jose CA
Yan Yan Tang - Mountain View CA

Sun Microsystems, Inc. - Santa Clara CA

G09G 536

345557, 345531, 345554, 345556, 345559, 711122

An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.

6795078, Sep 21, 2004

Jan 31, 2002

10/066397

Michael G. Lavelle - Saratoga CA
Ewa M. Kubalska - San Jose CA
Yan Y. Tang - Mountain View CA

Sun Microsystems, Inc. - Santa Clara CA

G06G 1318

345535, 345537, 345557

A memory interface controls read and write accesses to a memory device. The memory device includes a level-one cache, level-two cache and storage cell array. The memory interface includes a data request processor (DRP), a memory control processor (MCP) and a block cleansing unit (BCU). The MCP controls transfers between the storage cell array, the level-two cache and the level-one cache. In response to a read request with associated read clear indication, the DRP controls a read from a level-one cache block, updates bits in a corresponding dirty tag, and sets a mode indicator of the dirty tag to a the read clear mode. The modified dirty tag bits and mode indicator are signals to the BCU that the level-one cache block requires a source clear operation. The BCU commands the transfer of data from a color fill block in the level-one cache to the level-two cache.

6795081, Sep 21, 2004

May 18, 2001

09/861479

Michael G. Lavelle - Saratoga CA
Philip C. Leung - Fremont CA
Yan Y. Tang - Mountain View CA

Sun Microsystems, Inc. - Santa Clara CA

G09G 536

345557, 345537

A system and method capable of super-sampling and performing super-sample convolution are disclosed. In one embodiment, the system may comprise a graphics processor, a frame buffer, a sample cache, and a sample-to-pixel calculation unit. The graphics processor may be configured to generate a plurality of samples. The frame buffer, which is coupled to the graphics processor, may be configured to store the samples in a sample buffer. The samples may be positioned according to a regular grid, a perturbed regular grid, or a stochastic grid. The sample-to-pixel calculation unit is programmable to select a variable number of stored samples from the frame buffer, copy the selected samples to a sample cache, and filter a set of the selected samples into an output pixel. The sample-to-pixel calculation unit retains those samples in the sample cache that will be reused in a subsequent pixel calculation and replaces those samples no longer required with new samples for another filter calculation.

6803916, Oct 12, 2004

May 18, 2001

09/861475

Nandini Ramani - Saratoga CA
David C. Kehlet - Los Altos CA
Ewa M. Kubalska - San Jose CA
Michael G. Lavelle - Saratoga CA
Michael A. Wasserman - Redwood City CA
Kevin Tang - Union City CA
Yan Yan Tang - Mountain View CA

Sun Microsystems, Inc. - Santa Clara CA

G06T 120

345506, 345558

A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of samples bins. Individual samples may be selected from the bins according to different criteria such as memory bank allocation to improve utilization of the systems rendering pipeline. Since the arrays may have more bins than the number of evaluation units in the rendering pipeline, the samples from the bins may be stored to FIFO memories to allow invalid or empty samples (those outside the primitive being rendered) to be removed. The samples may then be filtered to form pixels that are displayable to form an image on a display device.

6806883, Oct 19, 2004

Mar 11, 2002

10/094930

Michael G. Lavelle - Saratoga CA
Yan Yan Tang - Mountain View CA

Sun Microsystems, Inc. - Santa Clara CA

G06F 1318

345535, 345520, 345534, 345545, 711 5, 711150, 711167

A graphics system may include a frame buffer, a processing device coupled to access data in the frame buffer, a frame buffer interface coupled to the frame buffer, and an output controller configured to assert a request for display data to provide to a display device. The frame buffer interface may receive the request for display data from the output controller and delay providing the request for display data to the frame buffer if the processing device is currently requesting access to a portion of the frame buffer targeted by the request for display data. For example, if the frame buffer includes several memory banks and the request for display data targets a first bank, the frame buffer interface may delay providing the request for display data to the frame buffer if the processing device is currently requesting access to the first bank.

6812929, Nov 2, 2004

Mar 11, 2002

10/094957

Michael G. Lavelle - Saratoga CA
Ewa M. Kubalska - San Jose CA
Yan Yan Tang - Mountain View CA

Sun Microsystems, Inc. - Santa Clara CA

G06F 1318

345535, 345537, 345557, 345545, 345540, 711122, 711142, 711 13

A graphics system may include a frame buffer that includes several sets of one or more memory banks and a cache. The frame buffer may load data from one of the memory banks into the cache in response to receiving a cache fill request. Each set of memory banks is accessible independently of each other set of memory banks. A frame buffer interface coupled to the frame buffer includes a plurality of cache fill request queues. Each cache fill request queue is configured to store one or more cache fill requests targeting a corresponding one of the sets of memory banks. The frame buffer interface is configured to select a cache fill request from one of the cache fill request queues that stores cache fill requests targeting a set of memory banks that is not currently being accessed and to provide the selected cache fill request to the frame buffer.