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Zhong Pan, 462611 Fairhauser Rd, Naperville, IL 60564

Zhong Pan Phones & Addresses

2611 Fairhauser Rd, Naperville, IL 60564   

San Jose, CA   

4400 Solano Park Cir, Davis, CA 95616    530-7562093   

1505 De Rose Way, San Jose, CA 95126    408-2806751   

Work

Position: Food Preparation and Serving Related Occupations

Education

Degree: Associate degree or higher

Mentions for Zhong Pan

Zhong Pan resumes & CV records

Resumes

Zhong Pan Photo 22

Principal Optical Engineer

Location:
Chicago, IL
Industry:
Telecommunications
Work:
Infinera
Principal Optical Engineer
Lupo Futures Jan 2014 - Jan 2016
Quant Developer
Infinera Jun 2006 - Dec 2013
Principal Hardware Development Engineer
Uc Davis Sep 2000 - Sep 2006
Graduate Student Researcher
Education:
University of California, Davis 2000 - 2006
Master of Science, Doctorates, Masters, Doctor of Philosophy, Computer Engineering
Tsinghua University 1995 - 2000
Bachelors, Bachelor of Science, Electronics Engineering
Jiangxi Normal University 1992 - 1995
Skills:
Matlab, Optical Fiber, Algorithms, Testing, Optics, Programming, Simulations, Python, C, Signal Processing, Labview, Debugging, Optical Communications, System Architecture, Embedded Systems, C++, Fpga, Wireless, Machine Learning, Wireless Technologies, Verilog, Optimization, Julia, Linux, Visual Basic .Net, C#, Multicharts .Net, Neuroshell Trader, Chaoshunter, Pandas, Mysql, Data Mining, Data Analysis
Zhong Pan Photo 23

Director Of Development Engineering

Location:
San Francisco, CA
Industry:
Telecommunications
Work:
Lumentum
Director of Development Engineering
Oclaro
Director of Hardware Engineering
Irixi Technologies, Inc Oct 2013 - Mar 2016
Vice President of R and D
Jdsu Jun 2004 - Oct 2013
Development Engineering Manager
Nova Crystals Jun 2001 - Jun 2004
Memeber of Technical Staff
Education:
Institute of Semiconductors
Doctorates, Doctor of Philosophy, Philosophy
Tokyo Institute of Technology
Skills:
Product Development, Optoelectronics, R&D, Characterization, Engineering, Manufacturing, Fiber Optics, Optics, Semiconductors, Research and Development, Photonics, Telecommunications, Product Management, Integration, Laser, Start Ups, Matlab, Process Simulation, Embedded Systems, Project Management, Cross Functional Team Leadership, Engineering Management, Simulations, Rf, Optical Fiber, Design of Experiments, Failure Analysis, Program Management, Physics, Design For Manufacturing, Electronics, Hardware Architecture
Languages:
English
Mandarin

Publications & IP owners

Us Patents

Avalanche Photodiode With Edge Breakdown Suppression

US Patent:
7834379, Nov 16, 2010
Filed:
Jul 15, 2008
Appl. No.:
12/173189
Inventors:
Zhong Pan - San Jose CA, US
David Venables - Sunnyvale CA, US
Craig Ciesla - Mountain View CA, US
Assignee:
JDS Uniphase Corporation - Milpitas CA
International Classification:
H01L 31/18
US Classification:
257185, 257 99, 257186, 257436, 257E31022, 257E31061, 257E31064, 438 69, 438 87, 438 91
Abstract:
The invention relates to an avalanche photodiode having enhanced gain uniformity enabled by a tailored diffused p-n junction profile. The tailoring is achieved by a two stage doping process incorporating a solid source diffusion in combination with conventional gas source diffusion. The solid source diffusion material is selected for its solubility to the dopant compared to the solubility of the multiplication layer to dopant. The solid source has a diameter between the first and second diffusion windows. Thus, there are three distinct diffusion regions during the second diffusion. The dopant in the multiplication layer at the edge region, the dopant from the solid source material with a relatively higher dopant concentration (limited by the solubility of the dopant in the solid source material) at the intermediate region, and the central region exposed to an infinite diffusion source from the solid source material as it is continually charged with new dopant from the external gas source. The result is that both the dopant concentration and the diffusion depth decrease gradually from the center to the edge of the device. This tailored diffusion profile enables control of the electric field distribution such that edge breakdown is suppressed.

Semiconductor Photodiode And Method Of Manufacture Thereof

US Patent:
7893464, Feb 22, 2011
Filed:
Mar 28, 2008
Appl. No.:
12/057937
Inventors:
Syn-Yem Hu - San Jose CA, US
Zhong Pan - San Jose CA, US
Assignee:
JDS Uniphase Corporation - Milpitas CA
International Classification:
H01L 29/73
US Classification:
257199, 257186, 257481
Abstract:
A method of manufacture of an avalanche photodiode involving a step of making a recess in a top window layer of an avalanche photodiode layer stack, such that a wall surrounding the recess runs smoothly and gradually from the level of the recess to the level of the window layer. Further, diffusing a dopant over the entire window layer area so as to form a p-n junction at the bottom of the recess, and providing a first electrical isolation region around the recess by buried ion implantation or wet oxidation in order to limit the flow of electrical current to the p-n junction. Forming an isolation trench around the photodiode and a second electrical isolation region by ion implantation into the trench such that the second electrical isolation region runs through the absorption layer of the photodiode.

Photodiode With High Esd Threshold

US Patent:
7948006, May 24, 2011
Filed:
Jun 1, 2009
Appl. No.:
12/476070
Inventors:
Zhong Pan - San Jose CA, US
David Venables - Sunnyvale CA, US
Assignee:
JDS Uniphase Corporation - Milpitas CA
International Classification:
H01L 23/60
US Classification:
257173, 257452, 257458, 257656, 257459, 257461, 257E31061, 257E29336, 257E3111
Abstract:
A photodetector with an improved electrostatic discharge damage threshold is disclosed, suitable for applications in telecommunication systems operating at elevated data rates. The photodetector may be a PIN or an APD fabricated in the InP compound semiconductor system. The increased ESD damage threshold is achieved by reducing the ESD induced current density in the photodetector by a suitable widening of the contact at a critical location, increasing the series resistance and promoting lateral current spreading by means of a current spreading layer.

Mesa-Type Photodetectors With Lateral Diffusion Junctions

US Patent:
8030684, Oct 4, 2011
Filed:
Jul 16, 2008
Appl. No.:
12/174079
Inventors:
Syn-Yem Hu - San Jose CA, US
Zhong Pan - San Jose CA, US
Assignee:
JDS Uniphase Corporation - Milpitas CA
International Classification:
H01L 31/107
US Classification:
257186, 257442, 257E31005, 438 72
Abstract:
The present invention relates to a stable mesa-type photodetector with lateral diffusion junctions. The invention has found that without resorting to the complicated regrowth approach, a simple Zn diffusion process can be used to create high-quality semiconductor junction interfaces at the exposed critical surface or to terminate the narrow-bandgap photon absorption layers. The invention converts the epi material layers near or at the vicinity of the etched mesa trench or etched mesa steps into a different dopant type through impurity diffusion process. Preferably the diffused surfaces are treated with a subsequent surface passivation. This invention can be applied to both top-illuminating and bottom-illuminating configurations.

Determination Of Channel Latency Within A Round-Trip Path

US Patent:
8064486, Nov 22, 2011
Filed:
Sep 7, 2007
Appl. No.:
11/852186
Inventors:
Zhong Pan - Davis CA, US
Assignee:
Infinera Corporation - Sunnyvale CA
International Classification:
H04J 3/06
H04B 17/00
H04B 10/08
H04B 10/00
US Classification:
370516, 398 25, 398156
Abstract:
The present invention provides a system, apparatus, and method for determining latency differences in channels within a link at a single test site. In particular, the method allows for a single transmitting device to determine distinct latency differences on both transmitter and receiver-side paths without requiring a terminating node on the other side of the connection. In other words, a switch is used, in lieu of such a terminating node, at the other side of the paths that switches at least one channel's content onto another channel and sends it back for a round trip on various transmitter-and-receiver-side-paths combinations. The present invention is based on round trip measurements and switching capability of the receiving node.

Sealed Semiconductor Device

US Patent:
8253175, Aug 28, 2012
Filed:
Jan 18, 2010
Appl. No.:
12/689112
Inventors:
Zhong Pan - San Jose CA, US
Craig Ciesla - Mountin View CA, US
International Classification:
H01L 23/28
US Classification:
257222, 257E21407, 438522
Abstract:
A sealed semiconductor device having reduced delamination of the sealing layer in high temperature, high humidity conditions is disclosed. The semiconductor device includes a substrate and a stack of device layers on the substrate sealed with a sealing layer. The upper surface of a street area of the substrate is oxidized so that the oxidized region extends under the sealing layer. The presence of the oxidized region of the upper surface of the substrate helps reduce the delamination, because the oxidized surface does not react with water to the same extent as a non-oxidized surface. The semiconductor devices remain sealed after dicing through the street area because the oxidized surface does not delaminate.

Method And Apparatus For Controlling An Output Of An Optical Amplifier

US Patent:
8325413, Dec 4, 2012
Filed:
Mar 25, 2010
Appl. No.:
12/732118
Inventors:
Abhijeet D. Deore - Sunnyvale CA, US
Andrew Q. Phan - San Jose CA, US
Zhong Pan - Davis CA, US
Assignee:
Infinera Corporation - Sunnyvale CA
International Classification:
H04B 10/17
H04B 10/12
US Classification:
359334, 3593413
Abstract:
A system is provided that includes optical amplifiers provided upstream from an optical add-drop multiplexer (OADM). One of the optical amplifiers may be a Raman amplifier that supplies amplified light to another optical amplifier, such as an erbium doped fiber amplifier (EDFA), which, in turn, further amplifies and feeds the light to an input of the OADM. During turn-up, for example, the EDFA may initially be disabled, the power of the pump lasers of the Raman amplifier may be gradually increased until light input to the EDFA exceeds a power threshold at which the EDFA can amplify the input light. Light supplied to the EDFA does not have an excessive amount of power. Accordingly, at this point, the gain of the EDFA may be appropriately adjusted and then activated to supply optical signals to the OADM. Such optical signals may have a low power but not too low so as to prevent proper operation of downstream EDFA. Moreover, these optical signal do not have power that is so high as to cause “spiking.

Super-Channel Assignment Using A Flexible Grid

US Patent:
8553725, Oct 8, 2013
Filed:
Sep 30, 2011
Appl. No.:
13/249642
Inventors:
Iftekhar Hussain - Santa Clara CA, US
Abinder Dhillon - Allen TX, US
Zhong Pan - San Jose CA, US
Marco E. Sosa - San Jose CA, US
Assignee:
Infinera Corporation - Sunnyvale CA
International Classification:
H04J 4/00
US Classification:
370478, 398 43, 398 55, 398 68, 398 69
Abstract:
A node is configured to receive an instruction to establish a channel having a bandwidth that corresponds to an operating spectrum an optical fiber; obtain information that identifies a channel spacing and a pointer that identifies where, within the spectrum, to establish bandwidth allocations; identify a group of bandwidth segments based on the spectrum and the channel spacing; and generate bit words that correspond to the bandwidth allocations, where the bit words includes bits that, when set to a value, cause sets of segments to be reserved within the spectrum, and where the sets of segments identify where the bandwidth allocations begin and end, within the spectrum, relative to the pointer.

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