Inventors:
Chung-Yuan Sun - San Jose CA, US
Tong Liu - San Jose CA, US
Zili Zhang - Fremont CA, US
Sheng Feng - Cupertino CA, US
Eddy C. Huang - San Jose CA, US
Naihui Liao - Taipei, TW
Assignee:
Actel Corporation - Mountain View CA
International Classification:
G01R 31/28
G06F 17/50
G06F 7/38
Abstract:
A method for testing FPGA routing circuitry having a plurality of first sets of tracks having programmably connectable individual track segments includes providing a global control signal to simultaneously turn on all of the programmable elements in at least two of the first sets of tracks, defining individual test inputs to apply to the first end of each of the at least two of the first sets of tracks, determining an expected logic result for a selected logical combination of the individual test inputs, applying the individual test inputs to the first end of each of the at least two of the first sets of tracks, performing the selected logical combination on the second ends of the at least two of the first sets of tracks to generate an actual logic result, and flagging an error if the actual result is not identical with the expected logic result.
