Andrei KhodakovskyBelmont, CA

7006088, Feb 28, 2006

Jan 30, 2002

10/066100

Igor Guskov - Ann Arbor MI, US
Andrei Khodakovsky - Pasadena CA, US
Peter Schröder - Pasadena CA, US
Wim Sweldens - New Providence NJ, US

California Institute of Technology - Pasadena CA

G06T 17/00

345420, 345423, 345440

A method of forming a hybrid mesh representation of an object surface is provided, along with the hybrid mesh representation and data structures corresponding to various polygons in the hybrid mesh representation. The hybrid mesh representation comprises a base mesh and one or more higher level meshes. At least one of the higher level meshes representing a patch is an irregular mesh. The method of forming the hybrid mesh representation comprises the steps of forming a base mesh, and then forming one or more higher level meshes from the base mesh through one or more regular refinement operations in combination with at least one irregular operation.

7098916, Aug 29, 2006

Sep 19, 2002

10/252019

Andrei Khodakovsky - Pasadena CA, US
Peter Schroeder - Pasadena CA, US

California Institute of Technology - Pasadena CA

G06F 17/00
G06T 1/00
G06T 15/00
G06T 17/00
G06K 9/36
G06K 9/46
G06K 9/48

345428, 345419, 345418, 382232, 382241

Methods of connectivity encoding polygonal mesh representations of objects are described, along with methods of decoding encoded connectivity information for polygonal mesh representations of objects. In the encoding process, an active vertex queue is initialized with one or more vertices incident to a seed face. A vertex is selected from the queue, and the ring of the vertex traversed. If an unprocessed face is encountered during the traversal, the degree of the face, and the valences of any unprocessed vertices incident to the face are output. Any such unprocessed vertices are also entered into the queue. The method iterates until no more vertices remain on the active queue. In one implementation, an encoded data stream is output, which comprises two logical streams, one for face-degree information and the other for vertex-valence information. In the decoding process, the encoded data stream is received, and the connectivity of the mesh regenerated.

7315303, Jan 1, 2008

Oct 28, 2004

10/977555

Igor Guskov - Ann Arbor MI, US
Andrei Khodakovsky - Pasadena CA, US
Peter Schröder - Pasadena CA, US
Wim Sweldens - New Providence NJ, US

California Institute of Technology - Pasadena CA
Lucent Technologies, Inc. - Murray Hill NJ

G06T 15/30

345423, 345419, 345420, 345440

A method of forming a hybrid mesh representation of an object surface is provided, along with the hybrid mesh representation and data structures corresponding to various polygons in the hybrid mesh representation. The hybrid mesh representation comprises a base mesh and one or more higher level meshes. At least one of the higher level meshes representing a patch is an irregular mesh. The method of forming the hybrid mesh representation comprises the steps of forming a base mesh, and then forming one or more higher level meshes from the base mesh through one or more regular refinement operations in combination with at least one irregular operation.

8228337, Jul 24, 2012

Oct 3, 2008

12/245650

Andrei Khodakovsky - Belmont CA, US
Franck R. Diard - Mountain View CA, US

NVIDIA Corporation - Santa Clara CA

G06F 15/16
G06T 15/40
G09G 5/00

345502, 345422, 345620

One embodiment of the present invention sets forth a method for dynamically load balancing rendering operations across an IGPU and a DGPU. For each frame, the graphics driver configures the IGPU to pre-compute Z-values for a portion of the display surface and to write feedback data to the system memory indicating the time that the IGPU used to process the frame. The graphics driver then configures the DGPU to use the pre-computed Z-values while rendering to the complete display surface and to write feedback data to the system memory indicating the time that the DGPU used to process the frame. The graphics driver uses the feedback data from the IGPU and DGPU in conjunction with the percentage of the display surface that the IGPU Z-rendered for the frame to scale the portion of the display surface that the IGPU Z-renders for one or more subsequent frames. In this fashion, overall processing within the graphics pipeline is optimized across the IGPU and DGPU.

8427474, Apr 23, 2013

Oct 3, 2008

12/245639

Andrei Khodakovsky - Belmont CA, US
Franck R. Diard - Mountain View CA, US

Nvidia Corporation - Santa Clara CA

G06T 15/40
G06F 15/80

345422, 345505

One embodiment of the present invention sets forth a method for dynamically load balancing rendering operations across an IGPU and a DGPU. For each frame, the graphics driver configures the IGPU to pre-compute Z-values for a portion of the display surface and to write feedback data to the system memory indicating the time that the IGPU used to process the frame. The graphics driver then configures the DGPU to use the pre-computed Z-values while rendering to the complete display surface and to write feedback data to the system memory indicating the time that the DGPU used to process the frame. The graphics driver uses the feedback data from the IGPU and DGPU in conjunction with the percentage of the display surface that the IGPU Z-rendered for the frame to scale the portion of the display surface that the IGPU Z-renders for one or more subsequent frames. In this fashion, overall processing within the graphics pipeline is optimized across the IGPU and DGPU.

6995761, Feb 7, 2006

Sep 8, 2000

09/658214

Peter Schroeder - Altadena CA, US
Wim Sweldens - New Providence NJ, US
Andrei Khodakovsky - Santa Clara CA, US

California Institute of Technology - Pasadena CA
Lucent Technologies, Inc. - Murray Hill NJ

G06T 15/00

345419, 345423

A new progressive compression scheme for arbitrary topology, highly detailed and densely sampled meshes arising from geometry scanning. Meshes may have three distinct components: geometry, parameter, and connectivity information. The latter two do not contribute to the reduction of error in a compression setting. Using semi-regular meshes, parameter and connectivity information can be virtually eliminated. The semiregular meshes may be used with semi-regular wavelet transforms, zerotree coding, and subdivision based reconstruction.

2019020, Jul 4, 2019

Dec 28, 2017

15/857330

- Santa Clara CA, US
Kirill A. Dmitriev - Santa Clara CA, US
Andrei Khodakovsky - Belmont CA, US
Tzyywei Hwang - San Jose CA, US
Wishwesh Anil Gandhi - Sunnyvale CA, US
Lacky Vasant Shah - Los Altos Hills CA, US

G06T 1/60
G06T 1/20
G06F 12/1009
G06T 15/00

A method for rendering graphics frames allocates rendering work to multiple graphics processing units (GPUs) that are configured to allow access to pages of data stored in locally attached memory of a peer GPU. The method includes the steps of generating, by a first GPU coupled to a first memory circuit, one or more first memory access requests to render a first primitive for a first frame, where at least one of the first memory access requests targets a first page of data that physically resides within a second memory circuit coupled to a second GPU. The first GPU requests the first page of data through a first data link coupling the first GPU to the second GPU and a register circuit within the first GPU accumulates an access request count for the first page of data. The first GPU notifies a driver that the access request count has reached a specified threshold.

2019014, May 16, 2019

Feb 14, 2018

15/897090

- Santa Clara CA, US
Jack CHOQUETTE - Palo Alto CA, US
Manan PATEL - San Jose CA, US
Shirish GADRE - Fremont CA, US
Praveen KAUSHIK - Bengaluru, IN
Amanpreet GREWAL - Thornhill, CA
Shekhar DIVEKAR - Pune, IN
Andrei KHODAKOVSKY - San Carlos CA, US

G06F 9/455
G06F 8/41
G06F 9/38

A just-in-time (JIT) compiler binds constants to specific memory locations at runtime. The JIT compiler parses program code derived from a multithreaded application and identifies an instruction that references a uniform constant. The JIT compiler then determines a chain of pointers that originates within a root table specified in the multithreaded application and terminates at the uniform constant. The JIT compiler generates additional instructions for traversing the chain of pointers and inserts these instructions into the program code. A parallel processor executes this compiled code and, in doing so, causes a thread to traverse the chain of pointers and bind the uniform constant to a uniform register at runtime. Each thread in a group of threads executing on the parallel processor may then access the uniform constant.