Atish G Ghosh, 689606 Scenic Bluff Dr, Austin, TX 78733

6351724, Feb 26, 2002

Jan 10, 2001

09/758487

Steven R. Klassen - Austin TX
Atish Ghosh - Austin TX
Hans L. Magnusson - Buda TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 1130

702186, 702 80, 702180, 702187, 712227, 714 39, 714 30, 714 47

An apparatus and method are presented for monitoring the performance of a microprocessor. The apparatus includes performance monitoring hardware incorporated within the microprocessor. The performance monitoring hardware includes a memory unit for storing performance data. The memory unit includes multiple memory locations, each memory location being accessed by a unique set of address signals. Circuitry within the performance monitoring hardware produces the address signals. In one embodiment, the performance monitoring hardware includes an event select register array and circuitry for producing a set of high order (i. e. , most significant) address signals. The event select register array preferably includes several event select registers for storing binary codes corresponding to selected events. A performance data acquisition period is divided into multiple histogram time periods of equal length. The high order address signals partition the memory unit into sections.

7523243, Apr 21, 2009

Jun 21, 2006

11/425613

Mark R. Bohm - Village of Bear Creek TX, US
Atish Ghosh - Austin TX, US

Standard Microsystems Corporation - Hauppauge NY

G06F 13/00
G06F 13/14
G06F 13/36

710305, 710104, 710110, 710309

A shared USB device may be simultaneously configured and accessed by two or more USB hosts by using a multi-host capable device controller. The multi-host capable device may include separate upstream ports and buffers for each host, and may be configured with the capability to respond to USB requests from more than one host. The multi-host capable device may maintain a dedicated address, configuration, and response information for each host. Each host may therefore establish a dedicated USB connection with the sharing device without the sharing device having to be re-configured or re-enumerated each and every time the upstream hosts alternate accessing the USB device.

7627708, Dec 1, 2009

Dec 22, 2008

12/340957

Mark R. Bohm - Bear Creek TX, US
Atish Ghosh - Austin TX, US

Standard Microsystems Corporation - Hauppauge NY

G06F 13/00
G06F 13/14
G06F 13/36

710305, 710104, 710110, 710309

A USB device may be simultaneously configured and accessed by two or more USB hosts. The USB device may include separate upstream ports and buffers for each host, and a multi-host capable device controller configured to respond to simultaneous USB requests received from more than one host. The USB device may maintain a dedicated address, configuration, and response information for each host. The USB device may include a shared USB function block, and a multi-host controller configured to establish concurrent respective USB connections between the shared USB function block and two or more USB hosts, to allow the two or more USB hosts to simultaneously configure the USB device for the shared USB function. The multi-host controller may be configured to receive and respond to simultaneous respective USB access requests for the shared USB function sent by the two or more USB hosts.

8156352, Apr 10, 2012

Jan 27, 2009

12/360760

Atish Ghosh - Austin TX, US
Hans Magnusson - Austin TX, US

Standard Microsystems Corporation - Hauppauge NY

G06F 1/28

713300, 713340, 710305

A power controller for a peripheral bus interface. A peripheral bus power controller includes a first terminal, a second terminal coupled to receive an power enable input signal from a host controller, and a third terminal coupled to provide an over-current output signal indicative of an over-current condition to the host controller. The peripheral bus power controller further includes an enable circuit configured to assert a power enable output signal on the first terminal responsive to receiving the power enable input signal and a first buffer configured to provide the over-current output signal to the host controller responsive to the power controller detecting the over-current condition on the first terminal.

8321700, Nov 27, 2012

Dec 9, 2011

13/315868

Atish Ghosh - Austin TX, US
Hans Magnusson - Austin TX, US

Standard Microsystems Corporation - Hauppauge NY

G06F 1/28

713300, 713340, 710305

A power controller for a peripheral bus interface. A peripheral bus power controller includes a first terminal, a second terminal coupled to receive an power enable input signal from a host controller, and a third terminal coupled to provide an over-current output signal indicative of an over-current condition to the host controller. The peripheral bus power controller further includes an enable circuit configured to assert a power enable output signal on the first terminal responsive to receiving the power enable input signal and a first buffer configured to provide the over-current output signal to the host controller responsive to the power controller detecting the over-current condition on the first terminal.

2012005, Mar 1, 2012

Aug 26, 2010

12/868724

Atish Ghosh - Austin TX, US
Mark Bohm - Village Of Bear Creek TX, US

STANDARD MICROSYSTEMS CORPORATION - HAUPPAUGE NY

G06F 12/14
H04L 9/32

726 4, 726 3, 726 5

A method and system for securing access to a storage device including one or more locked logical sections. The method includes providing an interface device including a first port connected to a computing system and a second port connected to the storage device. Further, the method includes receiving a unique identifier from a wireless device, and deriving a key from the unique identifier. Based on the derived key, the method unlocks a logical section in the storage device. The method may further store access permission rights for the locked logical sections in the interface device and unlock the logical section based on the access permission rights. Moreover, the method may further authenticate the identity of a user of the wireless device for unlocking the storage device.

2013011, May 2, 2013

Oct 31, 2011

13/285202

Atish Ghosh - Austin TX, US
Matthew Kalibat - Austin TX, US

G06F 13/36

710315

Charging a device using a plurality of handshakes. A first device may provide a first handshake to a second device. A device of a first device type may be configured to charge its battery without further communication based on the first handshake. The first device may monitor a connection to the second device for a second handshake corresponding to a device of a second device type. In response to detecting the second handshake, the first device may provide a response to the second device. Accordingly, the second device of the second device type may be configured to charge its battery based on the second handshake.

5793941, Aug 11, 1998

Dec 4, 1995

8/566876

Jennifer B. Pencis - Austin TX
Atish Ghosh - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 1134

39518203

A primary cache test system is supplied using a secondary cache that closely matches specifications of the primary cache. Coherency is maintained between the primary and secondary caches using inclusion by a write-once protocol. The test system includes software which suspends cache operations on receipt of an error signal from a secondary cache controller or by periodically pausing cache operations for cache operation monitoring. During suspension of cache operations, the software verifies the states of the primary cache against the states and data within the secondary cache. Signals on cache hit and hit-modified pins that are available on the microprocessor integrated circuit are monitored to detect various error conditions. Error analysis includes detection of invalid hits to the primary cache, incorrectly modified lines in the primary cache and misses to the primary cache that should be hits.