Biao Zhang, 551871 The Alameda UNIT 350, San Jose, CA 95126

6452592, Sep 17, 2002

May 21, 2001

09/863239

Biao Zhang - Sunnyvale CA
Chin-Cheng Kau - Fremont CA

SmartASIC, Inc. - San Jose CA

G09G 500

345213, 345 99, 345132, 345204, 345 2, 348513, 348536, 348537

A method and circuit generates a sampling clock signal that digitizes an analog video signal. The sampling clock signal is generated by a clock divider coupled to the horizontal synchronization signal of the analog video signal. A divisor calculator calculates a divisor for the clock divider to control the frequency of the sampling clock signal. Specifically, the divisor calculator selects an initial divisor for the clock divider. Then the divisor calculator calculates a new divisor based on the target pixel value provided by a mode detector and the measured pixel value from a counter. Some embodiments of the present invention provides fine tuning of the frequency by testing other possible divisors with a plurality of different phases. In addition, some embodiments of the present invention calibrate the phase of the sampling clock signal to generate a phase shifted sampling clock signal.

6784944, Aug 31, 2004

Jun 19, 2001

09/885775

Biao Zhang - Sunnyvale CA
Jin Ji - Sunnyvale CA

SmartASIC, Inc. - San Jose CA

H04N 521

348607, 348619, 348622, 348620, 382262

A method and system of noise filtering is provided. The pixels of a first filter mask are separated into groups based on luminance. . . The sizes of each group is determined and a largest group is selected. The distance of each group of pixels from the largest group is also calculated. Pixels in groups that are small compared to the largest group and far from the largest group are tagged as noisy. After tagging the noisy pixels, additional filtering can be applied to the pixels of first filter mask without degradation from the tagged pixels.

7030934, Apr 18, 2006

Oct 18, 2002

10/274492

Shing-Jong Shy - Jubei, TW
Biao Zhang - Sunnyvale CA, US

Huaya Microelectronics, Ltd. - San Jose CA

H04N 5/46

348584, 348598, 348581, 348564, 348555, 382299

A video system and method for combining multiple video signals on a single display is provided. The video system includes a video processor to process a second video signal and generate a processed video signal. The processed video signal has the same resolution and scan rates as a first video signal. A multiplexer is used to selectively display either the processed video signal or the first video signal on a display.

6310618, Oct 30, 2001

Nov 13, 1998

9/190966

Biao Zhang - Sunnyvale CA
Chin-Cheng Kau - Fremont CA

SmartASIC, Inc. - San Jose CA

G09G 500

345213

A method and circuit generates a sampling clock signal that digitizes an analog video signal. The sampling clock signal is generated by a clock divider coupled to the horizontal synchronization signal of the analog video signal. A divisor calculator calculates a divisor for the clock divider to control the frequency of the sampling clock signal. Specifically, the divisor calculator selects an initial divisor for the clock divider. Then the divisor calculator calculates a new divisor based on the target pixel value provided by a mode detector and the measured pixel value from a counter. Some embodiments of the present invention fine tune the frequency by testing other possible divisors with a plurality of different phases. In addition, some embodiments of the present invention calibrate the phase of the sampling clock signal to generate a phase shifted sampling clock signal.