Philip T Cheng, 37San Diego, CA

6397343, May 28, 2002

Mar 19, 1999

09/273247

Ian M. Williams - Sunnyvale CA
Philip Cheng - San Jose CA

Microsoft Corporation - Redmond WA

G06F 108

713501

In a computer system having a CPU and a graphics subsystem, a device for dynamic graphics subsystem clock adjustment. A clock pulse generator is used for generating a clock frequency. The clock frequency is coupled to the graphics subsystem and is used by the graphics subsystem to synchronize and pace its internal operations. The clock frequency generated by the generator is variable over a range. A controller is coupled to the clock pulse generator, for adjusting the clock frequency from the clock pulse generator over the range. The controller interfaces with the computer system through an interface coupled to the controller. Through the interface, the controller communicates with the computer system or graphics subsystem and determines a load placed on the graphics subsystem. The controller adjusts the clock frequency generated by the clock pulse generator such that the clock frequency increases when the load on the graphics subsystem increases and the clock frequency decreases when the load on the graphics subsystem decreases, dynamically adjusting the clock frequency in response to the load on the graphics subsystem.

5196939, Mar 23, 1993

Dec 28, 1989

7/457988

Hamman Elabd - Sunnyvale CA
Martin K. S. Shih - San Jose CA
Philip C. Cheng - Cupertino CA

Loral Fairchild Corporation - Syosset NY

H04N 314
H04N 5335

35821311

The present invention is a method and apparatus for transferring data from an imaging device. An image array is used to capture an image arranged in columns and rows of charges held in pixels in the image array. These charges are then transferred through a group of vertical registers to a storage register. Once in the storage register rows which have not been selected for transfer are dumped to a dump drain. Rows that have been selected for transfer continue through the vertical registers until they reach a pair of transfer registers from which the rows are output.