Christopher Chi Cheng, 441640 Elmhurst Dr, Los Altos, CA 94024

6677831, Jan 13, 2004

Jan 31, 2001

09/773111

Christopher Cheng - Los Gatos CA
Josh Price - Livermore CA

3PARdata, Inc. - Fremont CA

H01P 502

333 34, 333 4, 333236

A new method to control differential signal trace impedance allows flexible use of different signal trace width and spacing while maintaining constant differential impedance in printed circuit boards. Differential impedance of a signal pair is determined by the geometry of individual traces and the spacing between traces. The value of the differential impedance is inversely proportional to signal trace width and directly proportional to signal trace spacing. By decreasing or increasing trace width and spacing simultaneously, a constant differential impedance can be achieved.

6834623, Dec 28, 2004

Aug 6, 2003

10/638461

Christopher T. Cheng - Mountain View CA, 94041

F02B 4310

123 1A, 123 3, 123DIG 12, 429 12, 423644, 423657

An embodiment of the present invention is a portable hydrogen generation system for operating a vehicle powered by either the hydrogen internal combustion engine or a fuel cell using active metals such as sodium potassium, magnesium, aluminum or iron in the form of an emulsion, and a method thereof. The emulsion comprises a metal powder pre-mixed with oil. In the case of sodium, potassium and magnesium, the metal is reacting with water at or near room temperature. However, in the case of aluminum and iron, the metal is reacting with alkali hydroxide solutions. The system is controlled and managed by a microprocessor in order to generate hydrogen on demand at or near room temperature with a very high efficiency.

6836815, Dec 28, 2004

Aug 8, 2001

09/925137

Stephen Clark Purcell - Mountain View CA
Christopher Thomas Cheng - Santa Clara CA

Pasternak Solutions LLC - Los Altos CA

G06F 1300

710317, 711148

A method and apparatus includes a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar; a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch crossbars each connected to a processor crossbar in each processor group, wherein no two switch crossbars in a switch group are connected to the same processor crossbar; a plurality of memory groups having a plurality of memory switch chips each having a plurality of memory controllers and a memory crossbar, each memory controller connected to the memory crossbar, each memory crossbar in each memory group connected to all of the switch crossbar in a corresponding one of the switch groups, wherein no two memory groups are connected to the same switch group.

7234018, Jun 19, 2007

Dec 27, 2004

11/023969

Stephen Clark Purcell - Mountain View CA, US
Christopher Thomas Cheng - Santa Clara CA, US

Pasternak Solutions LLC - Los Altos CA

G06F 13/00
G06F 12/00
G06T 1/00
G06T 1/60

710317, 711105, 711148

A method and apparatus includes a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar; a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch crossbars each connected to a processor crossbar in each processor group, wherein no two switch crossbars in a switch group are connected to the same processor crossbar; a plurality of memory groups having a plurality of memory switch chips each having a plurality of memory controllers and a memory crossbar, each memory controller connected to the memory crossbar, each memory crossbar in each memory group connected to all of the switch crossbar in a corresponding one of the switch groups, wherein no two memory groups are connected to the same switch group.

7457937, Nov 25, 2008

Feb 9, 2006

11/351652

Christopher T. Cheng - Santa Clara CA, US
Stephen C. Purcell - Mountain View CA, US

Nvidia Corporation - Santa Clara CA

G06F 12/00

711219, 711 5

Embodiments of the present invention recite a method and system for accessing data. In one embodiment of the present invention, a plurality of instances of data are stored in a memory device which comprises a plurality of memory modules disposed as an array of parallel columns. In response to receiving an indication that said plurality of instances of data is being accessed as a row of data, a first address translation table is accessed which describes the same row address in each of said plurality of memory modules wherein an instance of data is stored. Then, in response to receiving an indication that said plurality of instances of data is being accessed as a column of data, a second address translation table is accessed which describes a successive row address in each successive memory module wherein an instance of data is stored.

7508398, Mar 24, 2009

Aug 22, 2003

10/646076

John S. Montrym - Cupertino CA, US
Brian D. Hutsell - Milpitas CA, US
Steven E. Molnar - Chapel Hill NC, US
Gary M. Tarolli - Concord MA, US
Christopher T. Cheng - Santa Clara CA, US
Emmett M. Kilgariff - San Jose CA, US
Abraham B. de Waal - San Jose CA, US

NVIDIA Corporation - Santa Clara CA

G06F 12/10
G09G 5/36
G09G 5/00

345568, 345545, 345611

A system and method for providing antialiased memory access includes receiving a request to access a memory address. The memory address is examined to determine if the memory address is within a virtual frame buffer. If the memory address is within a virtual frame buffer then the memory address is transformed into one or more physical addresses within a frame buffer that is utilized for antialiasing. The frame buffer may be a single memory space containing subpixel information corresponding to pixels of the virtual frame buffer. Subpixels located at the physical addresses within the frame buffer are then accessed. The disclosed invention provides for direct access by a software application.

7565475, Jul 21, 2009

Aug 10, 2006

11/463842

Stephen Clark Purcell - Mountain View CA, US
Christopher Thomas Cheng - Santa Clara CA, US

Pasternak Solutions LLC - Los Altos CA

G06F 13/00

710317

Apparatus and methods are disclosed for processing memory transaction requests and memory transaction results between multiple processors and multiple shared memories, where the communications path between the multiple processors and shared memories is provided by a multi-stage crossbar network comprising a plurality of serially interconnected crossbar switches, wherein each of the crossbar switches independently assigns local memory transaction identifiers to each memory transaction request that it processes and uses the local memory transaction identifiers to match each received memory transaction result with its corresponding previously processed memory transaction request.

7622945, Nov 24, 2009

Dec 20, 2006

11/614031

Christopher Cheng - Cupertino CA, US
David Chu - Santa Clara CA, US

3PAR, Inc. - Fremont CA

H03K 19/003

326 21, 326 31, 326 82

A method for a mix mode driver to accommodate traces of different lengths includes sequentially shifting values of a data signal to a number of stages and sequentially amplifying the values of the data signal at least one stage. Depending on the length of trace for the data signal, the method further includes providing at least one amplifying coefficient to at least one stage and coupling a subset of the stages to an adder. The method finally includes outputting the data signal from the adder to the trace.