David Emerson Brereton, 621504 Shady Hillside Pass, Round Rock, TX 78664

4339797, Jul 13, 1982

Mar 26, 1980

6/133995

David A. Brereton - San Jose CA
Buddy F. Stansbury - San Jose CA

International Business Machines Corporation - Armonk NY

G06F 300

364200

A microcontroller is disclosed which executes all instructions in a fixed period machine cycle. A storage device is provided for storing data which is involved in the execution of instructions that are stored in a different memory device, such as a read only memory device. Specific locations in the data storage device are selected during execution of instructions by combining one partial storage address from two separate groups of partial storage address generators. One location "00" in the storage device is addressed automatically when no partial storage address generators are selected. An auxiliary register having a load control input terminal and the write input to the storage device are connected to a common source of data so that in response to certain instructions, the same data is entered into location "00" of the storage device and the auxiliary register from the data source during one fixed period machine cycle. A data path is also provided from the output of the auxiliary register to permit the auxiliary register to function as a partial storage address generator, and the path also extends through an ALU unit connected to the input of the data source to permit the original contents of the auxiliary register to be incremented during execution of certain other instructions.

4276595, Jun 30, 1981

Jun 30, 1978

5/921147

David A. Brereton - San Jose CA
Buddy F. Stansbury - San Jose CA

International Business Machines Corporation - Armonk NY

G06F 1300

364200

A microcontroller having a novel addressing arrangement for addressing a storage means containing microinstructions is disclosed. The microcontroller has a fixed machine cycle time for executing each instruction and is arranged to fetch the next instruction during the execution of the current instruction. Branch, conditional branch and non-branch type of instructions are executed. The means for executing instructions is characterized by a plurality of instruction addressable data sources which are selectively connected to the input of the ALU register during the input phase of the machine cycle and a plurality of instruction addressable data destinations which are selectively connected to the output of the ALU register during the output phase of the machine cycle. The means for fetching the next instruction is characterized by a plurality of partial address generators, one of which is the ALU register employed to transfer data from a source to a destination. Control means responsive to the contents of an instruction register decoder supplies appropriate control signals at predetermined times to cause the transfer of address signals from the partial address generators to the address register to initiate readout of the next instruction from the instruction storage means during the execution of the current instruction.

4348721, Sep 7, 1982

Mar 26, 1980

6/133991

David A. Brereton - San Jose CA
Buddy F. Stansbury - San Jose CA

International Business Machines Corporation - Armonk NY

G06F 922

364200

An improved arrangement is disclosed for storing link address data which is generated by a microcontroller during the execution of a program which involves a series of nested link type instructions and for returning the stored link address data under program control so that the program may be returned to a selected one of a plurality of branch points. The improved arrangement involves memory addressing circuitry for addressing a memory which stores instructions, a storage device for storing link addresses which are transferred from the memory address circuitry to the storage device when link type instructions are executed, storage addressing circuitry which controls the location in the storage device where the link address data is stored, control circuitry which is responsive to one instruction having a predefined field, the value of which is determined by the microprogrammer and which determines which of the nested link address data is to be returned to the memory addressing circuitry.

4339796, Jul 13, 1982

Mar 26, 1980

6/133993

David A. Brereton - San Jose CA
Buddy F. Stansbury - San Jose CA

International Business Machines Corporation - Armonk NY

G06F 922

364200

A system is disclosed for a microcontroller which permits the interruption of a sequence of instructions, each of which are executable in a fixed machine cycle in response to one of a plurality of interrupt/trap signals. The microcontroller is interrupted for one fixed period machine cycle, during which period one of a plurality of instructions are read out from an instruction storage location of a memory determined by the active interrupt/trap signal concurrently as data stored in separate registers, which define the condition of the microcontroller at the point of interruption, are transferred to one group of locations in a storage device which is different than the memory which stores the instruction. After the transfer, another group of storage locations also determined by the active trap request signal is available to instructions which executed in subsequent machine cycles. The system further responds to a set machine level instruction of the microcontroller which functions to transfer the data defining the previous condition of the microcontroller at the point of interruption which has been stored in the storage device back to the plurality of registers.

4339795, Jul 13, 1982

Mar 26, 1980

6/133992

David A. Brereton - San Jose CA
Buddy F. Stansbury - San Jose CA

International Business Machines Corporation - Armonk NY

G06F 300

364200

A microcontroller is disclosed for controlling the bidirectional transfer of data between two external units. The external units supply data to the microcontroller selectively on a plurality of input byte busses and receive data from the microcontroller on a plurality of output byte busses. The microcontroller includes an input port including a plurality of instruction addressable input funnels, each adapted to be connected to one of the input busses, and an output port including a plurality of instruction addressable output registers, each adapted to be connected to one of the output busses. Also included are an ALU unit, an ALU register, a memory for storing instructions, an instruction register, an instruction register decoder, and control circuitry which causes the transfer of a byte of data from an addressed funnel through the ALU to the ALU register during a first portion of a fixed machine cycle, and from the ALU register to the external address register during the second portion of the machine cycle. The control circuitry causes selectively a first data path to be established during the first portion of the machine cycle between an addressed external funnel and the ALU register, and a second data path to be established from the output of the ALU register to the addressed external register during the second portion of the machine cycle. Load Register signals are generated at specified times to cause entry of data into the register.