Darin S Petkov, 46Brooklyn, NY
Darin Petkov Phones & Addresses
Brooklyn, NY
261 Ginko Ter, Sunnyvale, CA 94086
748 Mathilda Ave, Sunnyvale, CA 94085
135 Rio Robles, San Jose, CA 95134
85 Rio Robles, San Jose, CA 95134
Hayward, CA
Cambridge, MA
Santa Clara, CA
PO Box 60339, Sunnyvale, CA 94088
Mentions for Darin S Petkov
Publications & IP owners
Us Patents
Load/Store Operation Of Memory Misaligned Vector Data Using Alignment Register Storing Realigned Data Portion For Combining With Remaining Portion
US Patent:
7219212, May 15, 2007
Filed:
Feb 25, 2005
Appl. No.:
11/067106
Inventors:
Himanshu A. Sanghavi - Fremont CA, US
Earl A. Killian - Los Altos Hills CA, US
James Robert Kennedy - Boulder Creek CA, US
Darin S. Petkov - Hayward CA, US
Peng Tu - San Ramon CA, US
William A. Huffman - Los Gatos CA, US
Earl A. Killian - Los Altos Hills CA, US
James Robert Kennedy - Boulder Creek CA, US
Darin S. Petkov - Hayward CA, US
Peng Tu - San Ramon CA, US
William A. Huffman - Los Gatos CA, US
Assignee:
Tensilica, Inc. - Santa Clara CA
International Classification:
G06F 9/315
US Classification:
712 6, 712 4, 712225
Abstract:
A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maintaining the simplicity of programming and allowing efficient physical implementation. Most of the application code can be encoded using two sets of narrow size instructions to achieve high code density. Adding a third (and larger, i. e. VLIW) instruction size allows the architecture to encode multiple operations per instruction for the performance critical section of the code. Further, each operation of the VLIW format instruction can optionally be a SIMD operation that operates upon vector data. A scheme for the optimal utilization (highest achievable performance for the given amount of hardware) of multiply-accumulate (MAC) hardware is also provided.
Vector Co-Processor For Configurable And Extensible Processor Architecture
US Patent:
7376812, May 20, 2008
Filed:
May 13, 2002
Appl. No.:
10/145380
Inventors:
Himanshu A. Sanghavi - Fremont CA, US
Earl A. Killian - Los Altos Hills CA, US
James Robert Kennedy - Boulder Creek CA, US
Darin S. Petkov - Hayward CA, US
Peng Tu - San Ramon CA, US
William A. Huffman - Los Gatos CA, US
Earl A. Killian - Los Altos Hills CA, US
James Robert Kennedy - Boulder Creek CA, US
Darin S. Petkov - Hayward CA, US
Peng Tu - San Ramon CA, US
William A. Huffman - Los Gatos CA, US
Assignee:
Tensilica, Inc. - Santa Clara CA
International Classification:
G06F 15/00
G06F 15/76
G06F 15/76
US Classification:
712 24, 712 22, 712 23, 712 34, 712 35
Abstract:
A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maintaining the simplicity of programming and allowing efficient physical implementation. Most of the application code can be encoded using two sets of narrow size instructions to achieve high code density. Adding a third (and larger, i. e. VLIW) instruction size allows the architecture to encode multiple operations per instruction for the performance critical section of the code. Further, each operation of the VLIW format instruction can optionally be a SIMD operation that operates upon vector data. A scheme for the optimal utilization (highest achievable performance for the given amount of hardware) of multiply-accumulate (MAC) hardware is also provided.
Method And System For Automatic Generation Of Processor Datapaths Using Instruction Set Architecture Implementing Means
US Patent:
7590964, Sep 15, 2009
Filed:
Dec 19, 2005
Appl. No.:
11/313231
Inventors:
Darin Stemenov Petkov - San Jose CA, US
David William Goodwin - Los Altos CA, US
Dror Eliezer Maydan - Palo Alto CA, US
David William Goodwin - Los Altos CA, US
Dror Eliezer Maydan - Palo Alto CA, US
Assignee:
Tensilica, Inc. - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
716 18, 716 6, 716 13
Abstract:
Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The operations may also include one or more extension operations defined by one or more designers. Thus, a description of the behaviors of the various standard and/or extension operations that compose the ISA of an instance of a standard or configurable processor is used to automatically generate a set of shared processor datapaths that implement the behavior of those operations. In addition, certain aspects may take one or more operations as well as one or more input semantics and either re-implement the input semantics automatically, or combine the input semantics with each other or with one or more other operations to automatically generate a new set of shared processor datapaths.
Automatic Instruction Set Architecture Generation
US Patent:
7971197, Jun 28, 2011
Filed:
Aug 18, 2005
Appl. No.:
11/208239
Inventors:
David William Goodwin - Sunnyvale CA, US
Dror Maydan - Palo Alto CA, US
Ding-Kai Chen - San Jose CA, US
Darin Stamenov Petkov - Hayward CA, US
Steven Weng-Kiang Tjiang - Palo Alto CA, US
Peng Tu - San Ramon CA, US
Christopher Rowen - Santa Cruz CA, US
Dror Maydan - Palo Alto CA, US
Ding-Kai Chen - San Jose CA, US
Darin Stamenov Petkov - Hayward CA, US
Steven Weng-Kiang Tjiang - Palo Alto CA, US
Peng Tu - San Ramon CA, US
Christopher Rowen - Santa Cruz CA, US
Assignee:
Tensilica, Inc. - Santa Clara CA
International Classification:
G06F 9/45
G06F 15/00
G06F 15/76
G06F 15/00
G06F 15/76
US Classification:
717151, 712 3, 712 7, 712 24, 712 41, 712227
Abstract:
A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.
Method And System For Automatic Generation Of Processor Datapaths
US Patent:
8156464, Apr 10, 2012
Filed:
Apr 28, 2008
Appl. No.:
12/111153
Inventors:
Darin Stamenov Petkov - San Jose CA, US
David William Goodwin - Los Altos CA, US
Dror Eliezer Maydan - Palo Alto CA, US
David William Goodwin - Los Altos CA, US
Dror Eliezer Maydan - Palo Alto CA, US
Assignee:
Tensilica, Inc. - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
716113, 716104, 716136
Abstract:
Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The operations may also include one or more extension operations defined by one or more designers. Thus, a description of the behaviors of the various standard and/or extension operations that compose the ISA of an instance of a standard or configurable processor is used to automatically generate a set of shared processor datapaths that implement the behavior of those operations. In addition, certain aspects may take one or more operations as well as one or more input semantics and either re-implement the input semantics automatically, or combine the input semantics with each other or with one or more other operations to automatically generate a new set of shared processor datapaths.
Determination Of Transitional Characteristic Attributes Of Components During Scheduled Wake-Up Power Transition Of Computing Device
US Patent:
8560873, Oct 15, 2013
Filed:
Jan 13, 2011
Appl. No.:
13/006070
Inventors:
Chris Sosa - Sunnyvale CA, US
Darin Petkov - Sunnyvale CA, US
Sameer Nanda - San Jose CA, US
Darin Petkov - Sunnyvale CA, US
Sameer Nanda - San Jose CA, US
Assignee:
Google Inc. - Mountain View CA
International Classification:
G06F 1/32
US Classification:
713323, 712502
Abstract:
Apparatus and methods for gathering and analyzing operating statistics are disclosed. An example method includes automatically scheduling a wake-up event, where occurrence of the wake-up event, initiating, after scheduling the wake-up event, a transition of the computing device from an active power state to a low power state, initiating a transition of the computing device from the low power state to the active power state in response to occurrence of the scheduled wake-up event, gathering a first set of one or more operating statistics in response to the transition from the low power state to the active power state in response to occurrence of the wake-up event and analyzing the first set of one more operating statistics to determine one or more performance attributes of the computing device associated with the transitions between the low power state and the active power state.
Crash Data Handling
US Patent:
8621282, Dec 31, 2013
Filed:
May 19, 2011
Appl. No.:
13/111909
Inventors:
Kenneth E. Mixter - Mountain View CA, US
Darin S. Petkov - Sunnyvale CA, US
Darin S. Petkov - Sunnyvale CA, US
Assignee:
Google Inc. - Mountain View CA
International Classification:
G06F 11/00
US Classification:
714 3811, 726 26
Abstract:
Systems and methods for handling a crash of a process running on an operating system (OS) of a client are provided. In some aspects, a method includes generating crash data based on a dump file associated with the crash of the process. The crash data is associated with a first user logged in to the OS at the time of the crash. The method also includes storing the crash data in a cryptographically secure location on the client such that the crash data persists across reboot of the client. The method also includes preventing the crash data from being sent to an analysis server when the first user is not logged in to the OS.
Automatic Instruction Set Architecture Generation
US Patent:
2003007, Apr 17, 2003
Filed:
Oct 16, 2001
Appl. No.:
09/981291
Inventors:
David Goodwin - Sunnyvale CA, US
Dror Maydan - Palo Alto CA, US
Ding-Kai Chen - San Jose CA, US
Darin Petkov - Hayward CA, US
Steven Tjiang - Palo Alto CA, US
Peng Tu - San Ramon CA, US
Christopher Rowen - Santa Cruz CA, US
Dror Maydan - Palo Alto CA, US
Ding-Kai Chen - San Jose CA, US
Darin Petkov - Hayward CA, US
Steven Tjiang - Palo Alto CA, US
Peng Tu - San Ramon CA, US
Christopher Rowen - Santa Cruz CA, US
International Classification:
G06F009/45
G06F015/00
G06F015/76
G06F015/00
G06F015/76
US Classification:
717/161000, 717/156000, 712/004000, 712/024000, 712/036000
Abstract:
A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.
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