Edward C HepworthPhoenix, AZ

4087855, May 2, 1978

Sep 17, 1975

5/614109

Thomas H. Bennett - Scottsdale AZ
Earl F. Carlow - Scottsdale AZ
Edward C. Hepworth - Apache Junction AZ
Wilbur L. Mathys - Norristown PA
William D. Mensch - Norristown PA
Rodney H. Orgill - Norristown PA
Charles I. Peddle - Norristown PA
Michael F. Wiles - Phoenix AZ

Motorola, Inc. - Schaumburg IL

G06F 300
G06F 1300

364200

A digital system includes a microprocessor coupled to a data bus and an address bus. A memory for storing data and instructions is connected to the data bus and the address bus. A peripheral device is connected to an interface adaptor. The interface adaptor is connected to the data bus and the address bus, and performs the function of interfacing between the digital system and a peripheral device, such as a printer or a display device. The microprocessor includes logic circuitry for generating a Valid Memory Address (VMA) output. The VMA output is used to generate an enable signal applied to the memory and the adaptor to enable the memory and the adaptor to be accessed by the microprocessor when the binary address on the address bus is valid and to prevent the memory and the adaptor from being accessed by the microprocessor when the binary address on the address bus is not valid with respect to the microprocessor.

4086627, Apr 25, 1978

Sep 17, 1975

5/614110

Thomas H. Bennett - Scottsdale AZ
Earl F. Carlow - Scottsdale AZ
Edward C. Hepworth - Apache Junction AZ
Wilbur L. Mathys - Norristown PA
William D. Mensch - Norristown PA
Rodney H. Orgill - Norristown PA
Charles I. Peddle - Norristown PA
Michael F. Wiles - Phoenix AZ

Motorola, Inc. - Schaumburg IL

G06F 918

364200

A microprocessor system includes a microprocessor, a memory, and an interface adaptor all coupled to a data bus. The interface adaptor is coupled between the data bus and a peripheral device, such as a teleprinter. A first interrupt conductor is connected to the peripheral device and to interrupt logic circuitry in the interface adaptor. A second interrupt conductor is connected to the microprocessor and the interrupt logic circuitry. The interrupt logic circuitry is also coupled to and interrogatable by the microprocessor via the data bus. The interrupt logic circuitry stores interrupt contrl information from the data bus, and generates a second interrupt signal on the second interrupt conductor in response to the stored interrupt control information and an interrupt signal generated on the first interrupt conductor by the peripheral device. The interrupt logic circuitry also stores status information indicative of the occurrence of the first interrupt signal and effects interrogation of that status via the data bus.

4071887, Jan 31, 1978

Oct 30, 1975

5/627180

Thomas C. Daly - Phoenix AZ
Edward C. Hepworth - Chattanooga TN
Rodney J. Means - Manassas VA

Motorola, Inc. - Schaumburg IL

G06F 300
H04J 300

364200

An integrated circuit synchronous data adaptor (SSDA) provides a bidirectional interface for synchronous data interchange. Internal control and interface logic including first-in-first-out (FIFO) buffer memory enables simultaneous transmitting and receiving of standard synchronous communication characters to allow data transfer between serial data channels and the parallel bidirectional data bus of a bus organized system such as a microprocessor (MPU) system. Parallel data from the bus system is serially transmitted and received by the SSDA with synchronization character insertion and deletion, fill character insertion and deletion, parity generation and error checking. The functional configuration of the SSDA is programmed via the MPU system data bus during system initialization and can be reconfigured via program control during subsequent system operation. Programmable control registers provide control for variable word lengths, transmit control, receive control, synchronization control, and interrupt control. Status, timing and control lines provide peripheral unit or modem control.

4218740, Aug 19, 1980

Jan 5, 1977

5/757120

Thomas H. Bennett - Scottsdale AZ
Earl F. Carlow - Scottsdale AZ
Edward C. Hepworth - Apache Junction AZ
William D. Mensch - Norristown PA
Charles I. Peddle - Norristown PA
Gene A. Schriber - Tempe AZ
Michael F. Wiles - Phoenix AZ

Motorola, Inc. - Schaumburg IL

G06F 300

364200

A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA. The peripheral interface adaptor includes a plurality of system data bus buffer circuits coupled to a system data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. The direction of data flow in the peripheral data bus is controlled by a data direction register. Data from the system data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, a data direction register and a data register. Data from the peripheral data bus, the data direction register and the control register are transferred via an output bus to the system data bus buffers. Control signals are generated by select, read/write control, and register select logic which provides signals on a control bus coupled to the input register, the data register, the control register, and the data direction register to control data transfers between the various buses, registers, and buffer circuits.

4020472, Apr 26, 1977

Sep 17, 1975

5/614114

Thomas H. Bennett - Scottsdale AZ
Earl F. Carlow - Scottsdale AZ
Edward C. Hepworth - Apache Junction AZ
Wilbur L. Mathys - Norristown PA
William D. Mensch - Norristown PA
Rodney H. Orgill - Norristown PA
Charles I. Peddle - Norristown PA
Michael F. Wiles - Phoenix AZ

Motorola, Inc. - Chicago IL

G06F 300

3401725

An interface adaptor suitable for use in a microprocessor system includes an input register coupled to a bidirectional data bus of the microprocessor system. The interface adaptor includes a plurality of registers, including a control register and a data register, coupled to the input register by means of an internal input bus. Each of the plurality of registers includes flip-flops which are coupled as slave flip-flops to corresponding flip-flops of the input register. The corresponding flip-flops of the input register function as master flip-flops. The interface adaptor also includes register selection logic circuitry for selecting one of the plurality of registers by electrically coupling its slave flip-flop to the corresponding master flip-flops of the input register.

4263650, Apr 21, 1981

Jan 30, 1979

6/007752

Thomas H. Bennett - Scottsdale AZ
Earl F. Carlow - Scottsdale AZ
Edward C. Hepworth - Apache Junction AZ
Wilbur L. Mathys - Norristown PA
William D. Mensch - Norristown PA
Rodney H. Orgill - Norristown PA
Charles I. Peddle - Norristown PA
Michael F. Wiles - Phoenix AZ

Motorola, Inc. - Schaumburg IL

G06F 304
G06F 900
G06F 1300

364200

A digital system including a plurality of metal-oxide-semiconductor (MOS) chip random access memories (RAM), read only memories (ROM) and peripheral interface adaptors coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU). Each peripheral interface adaptor includes a control register loadable under program control. The contents of the control register control selection of several registers within the interface adaptor. The control register also controls other functions of the peripheral interface adaptor, including determining direction of data movement at the peripheral buffers of the interface adaptor. The contents of the control register of each interface adaptor are monitorable by the microprocessor unit.