Dong Qing Chen, 5111 Manning St, Manchester, NH 03103

7185226, Feb 27, 2007

Feb 25, 2002

10/469002

Dong Chen - Croton On Hudson NY, US
Paul W. Coteus - Yorktown Heights NY, US
Alan G. Gara - Mount Kisco NY, US
Todd E. Takken - Mount Kisco NY, US

International Business Machines Corporation - Armonk NY

G06F 11/20
G06F 11/00

714 13, 714 10, 712 12, 712 15

A multiprocessor, parallel computer is made tolerant to hardware failures by providing extra groups of redundant standby processors and by designing the system so that these extra groups of processors can be swapped with any group which experiences a hardware failure. This swapping can be under software control, thereby permitting the entire computer to sustain a hardware failure but, after swapping in the standby processors, to still appear to software as a pristine, fully functioning system.

7210088, Apr 24, 2007

Feb 25, 2002

10/468996

Dong Chen - Croton On Hudson NY, US
Paul W. Coteus - Yorktown Heights NY, US
Alan G. Gara - Mount Kisco NY, US

International Business Machines Corporation - Armonk NY

G06F 11/00
G06F 13/00
G06F 7/02
H03M 13/00

714746, 714758, 714807, 714819

A fault isolation technique for checking the accuracy of data packets transmitted between nodes of a parallel processor. An independent crc is kept of all data sent from one processor to another, and received from one processor to another. At the end of each checkpoint, the crcs are compared. If they do not match, there was an error. The crcs may be cleared and restarted at each checkpoint. In the preferred embodiment, the basic functionality is to calculate a CRC of all packet data that has been successfully transmitted across a given link. This CRC is done on both ends of the link, thereby allowing an independent check on all data believed to have been correctly transmitted. Preferably, all links have this CRC coverage, and the CRC used in this link level check is different from that used in the packet transfer protocol. This independent check, if successfully passed, virtually eliminates the possibility that any data errors were missed during the previous transfer period.

7486619, Feb 3, 2009

Mar 4, 2004

10/793068

Dong Chen - Croton On Hudson NY, US
Alan G. Gara - Mount Kisco NY, US
Mark E. Giampapa - Irvington NY, US
Philip Heidelberger - Cortlandt Manor NY, US
Dirk Hoenicke - Ossining NY, US
Pavlos M. Vranas - Bedford Hills NY, US
Matthias Augustin Blumrich - Ridgefield CT, US

International Business Machines Corporation - Armonk NY

H04L 12/28

370235, 370238

Multidimensional switch data networks are disclosed, such as are used by a distributed-memory parallel computer, as applied for example to computations in the field of life sciences. A distributed memory parallel computing system comprises a number of parallel compute nodes and a message passing data network connecting the compute nodes together. The data network connecting the compute nodes comprises a multidimensional switch data network of compute nodes having N dimensions, and a number/array of compute nodes Ln in each of the N dimensions. Each compute node includes an N port routing element having a port for each of the N dimensions. Each compute node of an array of Ln compute nodes in each of the N dimensions connects through a port of its routing element to an Ln port crossbar switch having Ln ports. Several embodiments are disclosed of a 4 dimensional computing system having 65,536 compute nodes.

7620841, Nov 17, 2009

Jan 19, 2006

11/335784

Dong Chen - Croton On Hudson NY, US
Alan Gara - Mount Kisco NY, US
Philip Heidelberger - Cortlandt Manor NY, US
Thomas Alan Liebsch - Rochester MN, US
Burkhard Steinmacher-Burow - Baden-Wuerttemburg, DE
Pavlos Michael Vranas - Bedford Hills NY, US

International Business Machines Corporation - Armonk NY

G06F 11/00

714 4, 714 10, 709226

A method and apparatus for re-utilizing partially failed compute resources in a massively parallel super computer system. In the preferred embodiments the compute node comprises a number of clock domains that can be enabled separately. When an error in a compute node is detected, and the failure is not in network communication blocks, a clock enable circuit enables the clocks to the network communication blocks only to allow the partially failed compute node to be re-utilized as a network resource. The computer system can then continue to operate with only slightly diminished performance and thereby improve performance and perceived overall reliability.

7694035, Apr 6, 2010

Jun 26, 2007

11/768781

Dong Chen - Croton on Hudson NY, US
Alan G. Gara - Mount Kisco NY, US
Philip Heidelberger - Cortlandt Manor NY, US
Pavlos Vranas - Danville CA, US

International Business Machines Corporation - Armonk NY

G06F 13/28
G06F 3/00
G06F 5/00

710 22, 710 52

A parallel computer system is constructed as a network of interconnected compute nodes. Each of the compute nodes includes at least one processor, a memory and a DMA engine. The DMA engine includes a processor interface for interfacing with the at least one processor, DMA logic, a memory interface for interfacing with the memory, a DMA network interface for interfacing with the network, injection and reception byte counters, injection and reception FIFO metadata, and status registers and control registers. The injection FIFOs maintain memory locations of the injection FIFO metadata memory locations including its current head and tail, and the reception FIFOs maintain the reception FIFO metadata memory locations including its current head and tail. The injection byte counters and reception byte counters may be shared between messages.

7701846, Apr 20, 2010

Jun 26, 2007

11/768572

Dong Chen - Croton On Hudson NY, US
Alan Gara - Mount Kisco NY, US
Philip Heidelberger - Cortlandt Manor NY, US
Pavlos Vranas - Danville CA, US

International Business Machines Corporation - Armonk NY

H04L 1/00

370216, 370242, 370248, 370250, 370252, 714 18

An apparatus and method for capturing data packets for analysis on a network computing system includes a sending node and a receiving node connected by a bi-directional communication link. The sending node sends a data transmission to the receiving node on the bi-directional communication link, and the receiving node receives the data transmission and verifies the data transmission to determine valid data and invalid data and verify retransmissions of invalid data as corresponding valid data. A memory device communicates with the receiving node for storing the invalid data and the corresponding valid data. A computing node communicates with the memory device and receives and performs an analysis of the invalid data and the corresponding valid data received from the memory device.

7765337, Jul 27, 2010

Jun 5, 2007

11/758167

Dong Chen - Croton on Hudson NY, US
Mark E. Giampapa - Irvington NY, US
Philip Heidelberger - Cortlandt Manor NY, US
Sameer Kumar - White Plains NY, US
Jeffrey J. Parker - Rochester MN, US
Burkhard D. Steinmacher-Burow - Esslingen, DE
Pavlos Vranas - Danville CA, US

International Business Machines Corporation - Armonk NY

G06F 13/28
G06F 3/00
G06F 13/00

710 22, 710 15, 710 19, 710 32

Methods, compute nodes, and computer program products are provided for direct memory access (‘DMA’) transfer completion notification. Embodiments include determining, by an origin DMA engine on an origin compute node, whether a data descriptor for an application message to be sent to a target compute node is currently in an injection first-in-first-out (‘FIFO’) buffer in dependence upon a sequence number previously associated with the data descriptor, the total number of descriptors currently in the injection FIFO buffer, and the current sequence number for the newest data descriptor stored in the injection FIFO buffer; and notifying a processor core on the origin DMA engine that the message has been sent if the data descriptor for the message is not currently in the injection FIFO buffer.

7802025, Sep 21, 2010

Jun 26, 2007

11/768795

Dong Chen - Croton on Hudson NY, US
Alan G. Gara - Mount Kisco NY, US
Mark E. Giampapa - Irvington NY, US
Philip Heidelberger - Cortlandt Manor NY, US
Burkhard Steinmacher-Burow - Esslingen, DE
Pavlos Vranas - Danville CA, US

International Business Machines Corporation - Armonk NY

G06F 13/28

710 22, 706 42, 709212, 709213

A parallel computer system is constructed as a network of interconnected compute nodes to operate a global message-passing application for performing communications across the network. Each of the compute nodes includes one or more individual processors with memories which run local instances of the global message-passing application operating at each compute node to carry out local processing operations independent of processing operations carried out at other compute nodes. Each compute node also includes a DMA engine constructed to interact with the application via Injection FIFO Metadata describing multiple Injection FIFOs where each Injection FIFO may containing an arbitrary number of message descriptors in order to process messages with a fixed processing overhead irrespective of the number of message descriptors included in the Injection FIFO.